STM32H750 memory region definitions. More...

Macros
#define	BSP_ITCM_BASE 0x00000000UL
	ITCM RAM base address (64KB, zero wait-state code)

#define	BSP_ITCM_SIZE (64 * 1024)

#define	BSP_DTCM_BASE 0x20000000UL
	DTCM RAM base address (128KB, zero wait-state data)

#define	BSP_DTCM_SIZE (128 * 1024)

#define	BSP_DTCM_OBC_BASE 0x20010000UL
	Upper DTCM for OBC application hot data (64KB, unprivileged RW)

#define	BSP_DTCM_OBC_SIZE (64 * 1024)

#define	BSP_RAM_D1_BASE 0x24000000UL
	AXI SRAM (RAM_D1) base address (512KB)

#define	BSP_RAM_D1_SIZE (512 * 1024)

#define	BSP_RAM_D2_BASE 0x30000000UL
	AHB SRAM (RAM_D2) base address (288KB)

#define	BSP_RAM_D2_SIZE (288 * 1024)

#define	BSP_RAM_D3_BASE 0x38000000UL
	AHB SRAM (RAM_D3) base address (64KB)

#define	BSP_RAM_D3_SIZE (64 * 1024)

#define	BSP_FLASH_BASE 0x08000000UL
	Internal Flash base address (128KB)

#define	BSP_FLASH_SIZE (128 * 1024)

#define	BSP_QSPI_BASE 0x90000000UL
	QSPI Flash base address (8MB external)

#define	BSP_QSPI_SIZE (8 * 1024 * 1024)

#define	BSP_PERIPH_BASE 0x40000000
	Peripheral base address (512MB)

#define	BSP_PERIPH_SIZE (512 * 1024 * 1024)

Detailed Description

STM32H750 memory region definitions.

See also: STM32H750 Reference Manual RM0433, Section 2.3

Macro Definition Documentation

◆ BSP_DTCM_BASE

#define BSP_DTCM_BASE 0x20000000UL

DTCM RAM base address (128KB, zero wait-state data)

Definition at line 31 of file mpu.h.

◆ BSP_DTCM_OBC_BASE

#define BSP_DTCM_OBC_BASE 0x20010000UL

Upper DTCM for OBC application hot data (64KB, unprivileged RW)

Definition at line 35 of file mpu.h.

◆ BSP_DTCM_OBC_SIZE

#define BSP_DTCM_OBC_SIZE (64 * 1024)

Definition at line 36 of file mpu.h.

◆ BSP_DTCM_SIZE

#define BSP_DTCM_SIZE (128 * 1024)

Definition at line 32 of file mpu.h.

◆ BSP_FLASH_BASE

#define BSP_FLASH_BASE 0x08000000UL

Internal Flash base address (128KB)

Definition at line 50 of file mpu.h.

◆ BSP_FLASH_SIZE

#define BSP_FLASH_SIZE (128 * 1024)

Definition at line 51 of file mpu.h.

◆ BSP_ITCM_BASE

#define BSP_ITCM_BASE 0x00000000UL

ITCM RAM base address (64KB, zero wait-state code)

Definition at line 27 of file mpu.h.

◆ BSP_ITCM_SIZE

#define BSP_ITCM_SIZE (64 * 1024)

Definition at line 28 of file mpu.h.

◆ BSP_PERIPH_BASE

#define BSP_PERIPH_BASE 0x40000000

Peripheral base address (512MB)

Definition at line 58 of file mpu.h.

◆ BSP_PERIPH_SIZE

#define BSP_PERIPH_SIZE (512 * 1024 * 1024)

Definition at line 59 of file mpu.h.

◆ BSP_QSPI_BASE

#define BSP_QSPI_BASE 0x90000000UL

QSPI Flash base address (8MB external)

Definition at line 54 of file mpu.h.

◆ BSP_QSPI_SIZE

#define BSP_QSPI_SIZE (8 * 1024 * 1024)

Definition at line 55 of file mpu.h.

◆ BSP_RAM_D1_BASE

#define BSP_RAM_D1_BASE 0x24000000UL

AXI SRAM (RAM_D1) base address (512KB)

Definition at line 38 of file mpu.h.

◆ BSP_RAM_D1_SIZE

#define BSP_RAM_D1_SIZE (512 * 1024)

Definition at line 39 of file mpu.h.

◆ BSP_RAM_D2_BASE

#define BSP_RAM_D2_BASE 0x30000000UL

AHB SRAM (RAM_D2) base address (288KB)

Definition at line 42 of file mpu.h.

◆ BSP_RAM_D2_SIZE

#define BSP_RAM_D2_SIZE (288 * 1024)

Definition at line 43 of file mpu.h.

◆ BSP_RAM_D3_BASE

#define BSP_RAM_D3_BASE 0x38000000UL

AHB SRAM (RAM_D3) base address (64KB)

Definition at line 46 of file mpu.h.

◆ BSP_RAM_D3_SIZE

#define BSP_RAM_D3_SIZE (64 * 1024)

Definition at line 47 of file mpu.h.

Macros