ICARUS OS (Intelligent Cooperative Architecture for Real-time Unified Systems) 0.1.0
Preemptive Real-Time Operating System for ARM Cortex-M7
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iwdg.c File Reference

Independent Watchdog (IWDG1) implementation. More...

#include "bsp/iwdg.h"
#include "stm32h7xx.h"

Go to the source code of this file.

Macros

#define IWDG_KEY_ENABLE   0xCCCCu
 
#define IWDG_KEY_REFRESH   0xAAAAu
 
#define IWDG_KEY_UNLOCK   0x5555u
 

Functions

void IWDG_Init (uint8_t prescaler, uint16_t reload)
 Configure and start the independent watchdog.
 
void IWDG_Refresh (void)
 Reload the watchdog counter ("kick" / "feed").
 
bool IWDG_WasReset (void)
 Was the most recent reset caused by the IWDG?
 
void IWDG_ClearResetFlag (void)
 Clear the IWDG reset flag in RCC->RSR.
 

Detailed Description

Independent Watchdog (IWDG1) implementation.

Direct CMSIS register access — the HAL IWDG module is left disabled in stm32h7xx_hal_conf.h to avoid pulling in the full HAL_IWDG state machine for what amounts to four register writes.

Register cheat-sheet (RM0433 §50):

IWDG1->KR write key register 0xCCCC = enable 0xAAAA = refresh (reload counter from RLR) 0x5555 = unlock PR/RLR/WINR for write access

IWDG1->PR 3-bit prescaler field [0..6] → div 4..256 IWDG1->RLR 12-bit reload value [1..4095] IWDG1->SR status: PVU (PR write pending), RVU (RLR pending), WVU (WINR pending) — must be 0 before we touch PR/RLR

The reset-reason side reads RCC->RSR (System Reset Status & Control Register on H7) — bit IWDG1RSTF tells us the previous boot was triggered by IWDG1. Cleared via the RMVF bit.

Author
Souham Biswas
Date
2026

Definition in file iwdg.c.

Macro Definition Documentation

◆ IWDG_KEY_ENABLE

#define IWDG_KEY_ENABLE   0xCCCCu

Definition at line 40 of file iwdg.c.

◆ IWDG_KEY_REFRESH

#define IWDG_KEY_REFRESH   0xAAAAu

Definition at line 41 of file iwdg.c.

◆ IWDG_KEY_UNLOCK

#define IWDG_KEY_UNLOCK   0x5555u

Definition at line 42 of file iwdg.c.

Function Documentation

◆ IWDG_ClearResetFlag()

void IWDG_ClearResetFlag ( void  )

Clear the IWDG reset flag in RCC->RSR.

Note
Safe to call unconditionally; clears the flag even if it was not set. Typically called once at boot after the application has logged the reset reason.

Definition at line 78 of file iwdg.c.

◆ IWDG_Init()

void IWDG_Init ( uint8_t  prescaler,
uint16_t  reload 
)

Configure and start the independent watchdog.

Parameters
prescalerOne of the IWDG_PRESCALER_* values (3-bit PR field).
reload12-bit reload value (1..4095). Total timeout is (reload + 1) × prescaler_div / LSI.
Note
Once started the IWDG cannot be stopped without a system reset. The function is idempotent — calling it twice with the same arguments is safe.

Definition at line 44 of file iwdg.c.

References IWDG_KEY_ENABLE, IWDG_KEY_REFRESH, IWDG_KEY_UNLOCK, and IWDG_PRESCALER_256.

◆ IWDG_Refresh()

void IWDG_Refresh ( void  )

Reload the watchdog counter ("kick" / "feed").

Note
Must be called periodically — at least once per timeout window — or the chip will reset.

Definition at line 70 of file iwdg.c.

References IWDG_KEY_REFRESH.

◆ IWDG_WasReset()

bool IWDG_WasReset ( void  )

Was the most recent reset caused by the IWDG?

Returns
true if the IWDGRST flag in RCC->RSR was set on this boot, false otherwise. The flag is sticky until cleared with IWDG_ClearResetFlag(), so this query is safe to call any number of times.

Definition at line 74 of file iwdg.c.