ICARUS OS (Intelligent Cooperative Architecture for Real-time Unified Systems) 0.1.0
Preemptive Real-Time Operating System for ARM Cortex-M7
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iwdg.c
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1
35#include "bsp/iwdg.h"
36
37#ifndef HOST_TEST
38#include "stm32h7xx.h"
39
40#define IWDG_KEY_ENABLE 0xCCCCu
41#define IWDG_KEY_REFRESH 0xAAAAu
42#define IWDG_KEY_UNLOCK 0x5555u
43
44void IWDG_Init(uint8_t prescaler, uint16_t reload) {
45 if (prescaler > IWDG_PRESCALER_256) {
46 prescaler = IWDG_PRESCALER_256;
47 }
48 if (reload == 0u) {
49 reload = 1u;
50 } else if (reload > 0x0FFFu) {
51 reload = 0x0FFFu;
52 }
53
54 /* Unlock PR/RLR for writing. */
55 IWDG1->KR = IWDG_KEY_UNLOCK;
56
57 /* Wait until any pending write to PR has propagated, then program. */
58 while ((IWDG1->SR & IWDG_SR_PVU) != 0u) { }
59 IWDG1->PR = prescaler;
60
61 /* Same for RLR. */
62 while ((IWDG1->SR & IWDG_SR_RVU) != 0u) { }
63 IWDG1->RLR = reload;
64
65 /* Reload + enable. The first KR=0xAAAA also locks PR/RLR back. */
66 IWDG1->KR = IWDG_KEY_REFRESH;
67 IWDG1->KR = IWDG_KEY_ENABLE;
68}
69
70void IWDG_Refresh(void) {
71 IWDG1->KR = IWDG_KEY_REFRESH;
72}
73
74bool IWDG_WasReset(void) {
75 return (RCC->RSR & RCC_RSR_IWDG1RSTF) != 0u;
76}
77
79 /* RMVF: writing 1 clears all reset reason flags in RCC->RSR. */
80 RCC->RSR |= RCC_RSR_RMVF;
81}
82
83#else /* HOST_TEST — software model so unit tests can exercise the API */
84
85#include <stdint.h>
86
87static uint8_t g_iwdg_started;
88static uint32_t g_iwdg_refresh_count;
89static bool g_iwdg_was_reset;
90
91void IWDG_Init(uint8_t prescaler, uint16_t reload) {
92 (void)prescaler;
93 (void)reload;
94 g_iwdg_started = 1u;
95 g_iwdg_refresh_count = 0u;
96}
97
98void IWDG_Refresh(void) {
99 if (g_iwdg_started != 0u) {
100 g_iwdg_refresh_count++;
101 }
102}
103
104bool IWDG_WasReset(void) {
105 return g_iwdg_was_reset;
106}
107
108void IWDG_ClearResetFlag(void) {
109 g_iwdg_was_reset = false;
110}
111
112/* ---- Test-only host hooks (not in iwdg.h; declared in test files) ----- */
113
114uint32_t __iwdg_host_refresh_count(void) {
115 return g_iwdg_refresh_count;
116}
117
118void __iwdg_host_set_reset_flag(bool value) {
119 g_iwdg_was_reset = value;
120}
121
122uint8_t __iwdg_host_started(void) {
123 return g_iwdg_started;
124}
125
126void __iwdg_host_reset_state(void) {
127 g_iwdg_started = 0u;
128 g_iwdg_refresh_count = 0u;
129 g_iwdg_was_reset = false;
130}
131
132#endif /* HOST_TEST */
#define IWDG_KEY_ENABLE
Definition iwdg.c:40
void IWDG_Init(uint8_t prescaler, uint16_t reload)
Configure and start the independent watchdog.
Definition iwdg.c:44
void IWDG_Refresh(void)
Reload the watchdog counter ("kick" / "feed").
Definition iwdg.c:70
bool IWDG_WasReset(void)
Was the most recent reset caused by the IWDG?
Definition iwdg.c:74
void IWDG_ClearResetFlag(void)
Clear the IWDG reset flag in RCC->RSR.
Definition iwdg.c:78
#define IWDG_KEY_UNLOCK
Definition iwdg.c:42
#define IWDG_KEY_REFRESH
Definition iwdg.c:41
#define IWDG_PRESCALER_256
Definition iwdg.h:53