ICARUS OS (Intelligent Cooperative Architecture for Real-time Unified Systems) 0.1.0
Preemptive Real-Time Operating System for ARM Cortex-M7
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lsm9ds1_reg.c
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1
20#include "lsm9ds1_reg.h"
21
49int32_t __weak lsm9ds1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52{
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63}
64
75int32_t __weak lsm9ds1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78{
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89}
90
103float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb)
104{
105 return ((float_t)lsb * 0.061f);
106}
107
108float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb)
109{
110 return ((float_t)lsb * 0.122f);
111}
112
113float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb)
114{
115 return ((float_t)lsb * 0.244f);
116}
117
118float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb)
119{
120 return ((float_t)lsb * 0.732f);
121}
122
123float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb)
124{
125 return ((float_t)lsb * 8.75f);
126}
127
128float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb)
129{
130 return ((float_t)lsb * 17.50f);
131}
132
133float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb)
134{
135 return ((float_t)lsb * 70.0f);
136}
137
138float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb)
139{
140 return ((float_t)lsb * 0.14f);
141}
142
143float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb)
144{
145 return ((float_t)lsb * 0.29f);
146}
147
148float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb)
149{
150 return ((float_t)lsb * 0.43f);
151}
152
153float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb)
154{
155 return ((float_t)lsb * 0.58f);
156}
157
158float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb)
159{
160 return (((float_t)lsb / 16.0f) + 25.0f);
161}
162
184int32_t lsm9ds1_gy_full_scale_set(const stmdev_ctx_t *ctx,
185 lsm9ds1_gy_fs_t val)
186{
187 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
188 int32_t ret;
189
190 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
191 (uint8_t *)&ctrl_reg1_g, 1);
192
193 if (ret == 0)
194 {
195 ctrl_reg1_g.fs_g = (uint8_t)val;
196 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
197 (uint8_t *)&ctrl_reg1_g, 1);
198 }
199
200 return ret;
201}
202
211int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx,
212 lsm9ds1_gy_fs_t *val)
213{
214 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
215 int32_t ret;
216
217 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
218 (uint8_t *)&ctrl_reg1_g, 1);
219
220 switch (ctrl_reg1_g.fs_g)
221 {
222 case LSM9DS1_245dps:
223 *val = LSM9DS1_245dps;
224 break;
225
226 case LSM9DS1_500dps:
227 *val = LSM9DS1_500dps;
228 break;
229
230 case LSM9DS1_2000dps:
231 *val = LSM9DS1_2000dps;
232 break;
233
234 default:
235 *val = LSM9DS1_245dps;
236 break;
237 }
238
239 return ret;
240}
241
251int32_t lsm9ds1_imu_data_rate_set(const stmdev_ctx_t *ctx,
252 lsm9ds1_imu_odr_t val)
253{
254 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
255 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
256 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
257 int32_t ret;
258
259 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
260 (uint8_t *)&ctrl_reg1_g, 1);
261
262 if (ret == 0)
263 {
264 ctrl_reg1_g.odr_g = (uint8_t)val & 0x07U;
265 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
266 (uint8_t *)&ctrl_reg1_g, 1);
267 }
268
269 if (ret == 0)
270 {
271 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
272 (uint8_t *)&ctrl_reg6_xl, 1);
273 }
274
275 if (ret == 0)
276 {
277 ctrl_reg6_xl.odr_xl = (((uint8_t)val & 0x70U) >> 4);
278 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
279 (uint8_t *)&ctrl_reg6_xl, 1);
280 }
281
282 if (ret == 0)
283 {
284 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
285 (uint8_t *)&ctrl_reg3_g, 1);
286 }
287
288 if (ret == 0)
289 {
290 ctrl_reg3_g.lp_mode = (((uint8_t)val & 0x80U) >> 7);
291 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
292 (uint8_t *)&ctrl_reg3_g, 1);
293 }
294
295 return ret;
296}
297
307int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx,
308 lsm9ds1_imu_odr_t *val)
309{
310 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
311 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
312 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
313 int32_t ret;
314
315 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
316 (uint8_t *)&ctrl_reg1_g, 1);
317
318 if (ret == 0)
319 {
320 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
321 (uint8_t *)&ctrl_reg6_xl, 1);
322 }
323
324 if (ret == 0)
325 {
326 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
327 (uint8_t *)&ctrl_reg3_g, 1);
328 }
329
330 switch ((ctrl_reg3_g.lp_mode << 7) | (ctrl_reg6_xl.odr_xl << 4) |
331 ctrl_reg1_g.odr_g)
332 {
333 case LSM9DS1_IMU_OFF:
334 *val = LSM9DS1_IMU_OFF;
335 break;
336
337 case LSM9DS1_GY_OFF_XL_10Hz:
338 *val = LSM9DS1_GY_OFF_XL_10Hz;
339 break;
340
341 case LSM9DS1_GY_OFF_XL_50Hz:
342 *val = LSM9DS1_GY_OFF_XL_50Hz;
343 break;
344
345 case LSM9DS1_GY_OFF_XL_119Hz:
346 *val = LSM9DS1_GY_OFF_XL_119Hz;
347 break;
348
349 case LSM9DS1_GY_OFF_XL_238Hz:
350 *val = LSM9DS1_GY_OFF_XL_238Hz;
351 break;
352
353 case LSM9DS1_GY_OFF_XL_476Hz:
354 *val = LSM9DS1_GY_OFF_XL_476Hz;
355 break;
356
357 case LSM9DS1_GY_OFF_XL_952Hz:
358 *val = LSM9DS1_GY_OFF_XL_952Hz;
359 break;
360
361 case LSM9DS1_XL_OFF_GY_14Hz9:
362 *val = LSM9DS1_XL_OFF_GY_14Hz9;
363 break;
364
365 case LSM9DS1_XL_OFF_GY_59Hz5:
366 *val = LSM9DS1_XL_OFF_GY_59Hz5;
367 break;
368
369 case LSM9DS1_XL_OFF_GY_119Hz:
370 *val = LSM9DS1_XL_OFF_GY_119Hz;
371 break;
372
373 case LSM9DS1_XL_OFF_GY_238Hz:
374 *val = LSM9DS1_XL_OFF_GY_238Hz;
375 break;
376
377 case LSM9DS1_XL_OFF_GY_476Hz:
378 *val = LSM9DS1_XL_OFF_GY_476Hz;
379 break;
380
381 case LSM9DS1_XL_OFF_GY_952Hz:
382 *val = LSM9DS1_XL_OFF_GY_952Hz;
383 break;
384
385 case LSM9DS1_IMU_14Hz9:
386 *val = LSM9DS1_IMU_14Hz9;
387 break;
388
389 case LSM9DS1_IMU_59Hz5:
390 *val = LSM9DS1_IMU_59Hz5;
391 break;
392
393 case LSM9DS1_IMU_119Hz:
394 *val = LSM9DS1_IMU_119Hz;
395 break;
396
397 case LSM9DS1_IMU_238Hz:
398 *val = LSM9DS1_IMU_238Hz;
399 break;
400
401 case LSM9DS1_IMU_476Hz:
402 *val = LSM9DS1_IMU_476Hz;
403 break;
404
405 case LSM9DS1_IMU_952Hz:
406 *val = LSM9DS1_IMU_952Hz;
407 break;
408
409 case LSM9DS1_XL_OFF_GY_14Hz9_LP:
410 *val = LSM9DS1_XL_OFF_GY_14Hz9_LP;
411 break;
412
413 case LSM9DS1_XL_OFF_GY_59Hz5_LP:
414 *val = LSM9DS1_XL_OFF_GY_59Hz5_LP;
415 break;
416
417 case LSM9DS1_XL_OFF_GY_119Hz_LP:
418 *val = LSM9DS1_XL_OFF_GY_119Hz_LP;
419 break;
420
421 case LSM9DS1_IMU_14Hz9_LP:
422 *val = LSM9DS1_IMU_14Hz9_LP;
423 break;
424
425 case LSM9DS1_IMU_59Hz5_LP:
426 *val = LSM9DS1_IMU_59Hz5_LP;
427 break;
428
429 case LSM9DS1_IMU_119Hz_LP:
430 *val = LSM9DS1_IMU_119Hz_LP;
431 break;
432
433 default:
434 *val = LSM9DS1_IMU_OFF;
435 break;
436 }
437
438 return ret;
439}
440
449int32_t lsm9ds1_gy_orient_set(const stmdev_ctx_t *ctx,
450 lsm9ds1_gy_orient_t val)
451{
452 lsm9ds1_orient_cfg_g_t orient_cfg_g;
453 int32_t ret;
454
455 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ORIENT_CFG_G,
456 (uint8_t *)&orient_cfg_g, 1);
457
458 if (ret == 0)
459 {
460 orient_cfg_g.orient = val.orient;
461 orient_cfg_g.signx_g = val.signx_g;
462 orient_cfg_g.signy_g = val.signy_g;
463 orient_cfg_g.signz_g = val.signz_g;
464 ret = lsm9ds1_write_reg(ctx, LSM9DS1_ORIENT_CFG_G,
465 (uint8_t *)&orient_cfg_g, 1);
466 }
467
468 return ret;
469}
470
479int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx,
480 lsm9ds1_gy_orient_t *val)
481{
482 lsm9ds1_orient_cfg_g_t orient_cfg_g;
483 int32_t ret;
484
485 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ORIENT_CFG_G,
486 (uint8_t *)&orient_cfg_g, 1);
487 val->orient = orient_cfg_g.orient;
488 val->signz_g = orient_cfg_g.signz_g;
489 val->signy_g = orient_cfg_g.signy_g;
490 val->signx_g = orient_cfg_g.signx_g;
491
492 return ret;
493}
494
503int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
504 uint8_t *val)
505{
506 lsm9ds1_status_reg_t status_reg;
507 int32_t ret;
508
509 ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
510 (uint8_t *)&status_reg, 1);
511 *val = status_reg.xlda;
512
513 return ret;
514}
515
524int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
525 uint8_t *val)
526{
527 lsm9ds1_status_reg_t status_reg;
528 int32_t ret;
529
530 ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
531 (uint8_t *)&status_reg, 1);
532 *val = status_reg.gda;
533
534 return ret;
535}
536
545int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
546 uint8_t *val)
547{
548 lsm9ds1_status_reg_t status_reg;
549 int32_t ret;
550
551 ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
552 (uint8_t *)&status_reg, 1);
553 *val = status_reg.tda;
554
555 return ret;
556}
557
566int32_t lsm9ds1_gy_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val)
567{
568 lsm9ds1_ctrl_reg4_t ctrl_reg4;
569 int32_t ret;
570
571 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
572
573 if (ret == 0)
574 {
575 ctrl_reg4.xen_g = val.xen_g;
576 ctrl_reg4.yen_g = val.yen_g;
577 ctrl_reg4.zen_g = val.zen_g;
578 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
579 }
580
581 return ret;
582}
583
592int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val)
593{
594 lsm9ds1_ctrl_reg4_t ctrl_reg4;
595 int32_t ret;
596
597 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
598 val->xen_g = ctrl_reg4.xen_g;
599 val->yen_g = ctrl_reg4.yen_g;
600 val->zen_g = ctrl_reg4.zen_g;
601
602 return ret;
603}
604
613int32_t lsm9ds1_xl_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val)
614{
615 lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
616 int32_t ret;
617
618 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
619 (uint8_t *)&ctrl_reg5_xl, 1);
620
621 if (ret == 0)
622 {
623 ctrl_reg5_xl.xen_xl = val.xen_xl;
624 ctrl_reg5_xl.yen_xl = val.yen_xl;
625 ctrl_reg5_xl.zen_xl = val.zen_xl;
626 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG5_XL,
627 (uint8_t *)&ctrl_reg5_xl, 1);
628 }
629
630 return ret;
631}
632
641int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val)
642{
643 lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
644 int32_t ret;
645
646 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
647 (uint8_t *)&ctrl_reg5_xl, 1);
648 val->xen_xl = ctrl_reg5_xl.xen_xl;
649 val->yen_xl = ctrl_reg5_xl.yen_xl;
650 val->zen_xl = ctrl_reg5_xl.zen_xl;
651
652 return ret;
653}
654
663int32_t lsm9ds1_xl_decimation_set(const stmdev_ctx_t *ctx,
664 lsm9ds1_dec_t val)
665{
666 lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
667 int32_t ret;
668
669 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
670 (uint8_t *)&ctrl_reg5_xl, 1);
671
672 if (ret == 0)
673 {
674 ctrl_reg5_xl.dec = (uint8_t)val;
675 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG5_XL,
676 (uint8_t *)&ctrl_reg5_xl, 1);
677 }
678
679 return ret;
680}
681
690int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx,
691 lsm9ds1_dec_t *val)
692{
693 lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl;
694 int32_t ret;
695
696 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG5_XL,
697 (uint8_t *)&ctrl_reg5_xl, 1);
698
699 switch (ctrl_reg5_xl.dec)
700 {
701 case LSM9DS1_NO_DECIMATION:
702 *val = LSM9DS1_NO_DECIMATION;
703 break;
704
705 case LSM9DS1_EVERY_2_SAMPLES:
706 *val = LSM9DS1_EVERY_2_SAMPLES;
707 break;
708
709 case LSM9DS1_EVERY_4_SAMPLES:
710 *val = LSM9DS1_EVERY_4_SAMPLES;
711 break;
712
713 case LSM9DS1_EVERY_8_SAMPLES:
714 *val = LSM9DS1_EVERY_8_SAMPLES;
715 break;
716
717 default:
718 *val = LSM9DS1_NO_DECIMATION;
719 break;
720 }
721
722 return ret;
723}
724
733int32_t lsm9ds1_xl_full_scale_set(const stmdev_ctx_t *ctx,
734 lsm9ds1_xl_fs_t val)
735{
736 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
737 int32_t ret;
738
739 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
740 (uint8_t *)&ctrl_reg6_xl, 1);
741
742 if (ret == 0)
743 {
744 ctrl_reg6_xl.fs_xl = (uint8_t)val;
745 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
746 (uint8_t *)&ctrl_reg6_xl, 1);
747 }
748
749 return ret;
750}
751
760int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx,
761 lsm9ds1_xl_fs_t *val)
762{
763 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
764 int32_t ret;
765
766 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
767 (uint8_t *)&ctrl_reg6_xl, 1);
768
769 switch (ctrl_reg6_xl.fs_xl)
770 {
771 case LSM9DS1_2g:
772 *val = LSM9DS1_2g;
773 break;
774
775 case LSM9DS1_16g:
776 *val = LSM9DS1_16g;
777 break;
778
779 case LSM9DS1_4g:
780 *val = LSM9DS1_4g;
781 break;
782
783 case LSM9DS1_8g:
784 *val = LSM9DS1_8g;
785 break;
786
787 default:
788 *val = LSM9DS1_2g;
789 break;
790 }
791
792 return ret;
793}
794
804int32_t lsm9ds1_block_data_update_set(const stmdev_ctx_t *ctx_mag,
805 stmdev_ctx_t *ctx_imu, uint8_t val)
806{
807 lsm9ds1_ctrl_reg8_t ctrl_reg8;
808 lsm9ds1_ctrl_reg5_m_t ctrl_reg5_m;
809 int32_t ret;
810
811 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
812 (uint8_t *)&ctrl_reg8, 1);
813
814 if (ret == 0)
815 {
816 ctrl_reg8.bdu = (uint8_t)val;
817 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
818 (uint8_t *)&ctrl_reg8, 1);
819 }
820
821 if (ret == 0)
822 {
823 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
824 (uint8_t *)&ctrl_reg5_m, 1);
825 }
826
827 if (ret == 0)
828 {
829 ctrl_reg5_m.fast_read = (uint8_t)(~val);
830 ctrl_reg5_m.bdu = (uint8_t)val;
831 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
832 (uint8_t *)&ctrl_reg5_m, 1);
833 }
834
835 return ret;
836}
837
847int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag,
848 stmdev_ctx_t *ctx_imu, uint8_t *val)
849{
850 lsm9ds1_ctrl_reg8_t ctrl_reg8;
851 lsm9ds1_ctrl_reg5_m_t ctrl_reg5_m;
852 int32_t ret;
853
854 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
855 (uint8_t *)&ctrl_reg8, 1);
856
857 if (ret == 0)
858 {
859 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG5_M,
860 (uint8_t *)&ctrl_reg5_m, 1);
861 *val = (uint8_t)(ctrl_reg5_m.bdu & ctrl_reg8.bdu);
862 }
863
864 return ret;
865}
866
877int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
878{
879 uint8_t buff[6];
880 int32_t ret;
881
882 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
883 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
884 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
885 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
886 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
887 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
888 ret = lsm9ds1_write_reg(ctx, LSM9DS1_OFFSET_X_REG_L_M, buff, 6);
889
890 return ret;
891}
892
903int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
904{
905 uint8_t buff[6];
906 int32_t ret;
907
908 ret = lsm9ds1_read_reg(ctx, LSM9DS1_OFFSET_X_REG_L_M, buff, 6);
909 val[0] = (int16_t)buff[1];
910 val[0] = (val[0] * 256) + (int16_t)buff[0];
911 val[1] = (int16_t)buff[3];
912 val[1] = (val[1] * 256) + (int16_t)buff[2];
913 val[2] = (int16_t)buff[5];
914 val[2] = (val[2] * 256) + (int16_t)buff[4];
915
916 return ret;
917}
918
927int32_t lsm9ds1_mag_data_rate_set(const stmdev_ctx_t *ctx,
928 lsm9ds1_mag_data_rate_t val)
929{
930 lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
931 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
932 lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m;
933 int32_t ret;
934
935 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
936 (uint8_t *)&ctrl_reg1_m, 1);
937
938 if (ret == 0)
939 {
940 ctrl_reg1_m.fast_odr = (((uint8_t)val & 0x08U) >> 3);
941 ctrl_reg1_m._do = ((uint8_t)val & 0x07U);
942 ctrl_reg1_m.om = (((uint8_t)val & 0x30U) >> 4);
943 ctrl_reg1_m.temp_comp = PROPERTY_ENABLE;
944 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_M,
945 (uint8_t *)&ctrl_reg1_m, 1);
946 }
947
948 if (ret == 0)
949 {
950 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M,
951 (uint8_t *)&ctrl_reg3_m, 1);
952 }
953
954 if (ret == 0)
955 {
956 ctrl_reg3_m.md = (((uint8_t)val & 0xC0U) >> 6);
957 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_M,
958 (uint8_t *)&ctrl_reg3_m, 1);
959 }
960
961 if (ret == 0)
962 {
963 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4_M,
964 (uint8_t *)&ctrl_reg4_m, 1);
965 }
966
967 if (ret == 0)
968 {
969 ctrl_reg4_m.omz = (((uint8_t)val & 0x30U) >> 4);;
970 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4_M,
971 (uint8_t *)&ctrl_reg4_m, 1);
972 }
973
974 return ret;
975}
976
985int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx,
986 lsm9ds1_mag_data_rate_t *val)
987{
988 lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
989 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
990 int32_t ret;
991
992 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
993 (uint8_t *)&ctrl_reg1_m, 1);
994
995 if (ret == 0)
996 {
997 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_M,
998 (uint8_t *)&ctrl_reg3_m, 1);
999 }
1000
1001 switch ((ctrl_reg3_m.md << 6) | (ctrl_reg1_m.om << 4) |
1002 (ctrl_reg1_m.fast_odr << 3) | ctrl_reg1_m._do)
1003 {
1004 case LSM9DS1_MAG_POWER_DOWN:
1005 *val = LSM9DS1_MAG_POWER_DOWN;
1006 break;
1007
1008 case LSM9DS1_MAG_LP_0Hz625:
1009 *val = LSM9DS1_MAG_LP_0Hz625;
1010 break;
1011
1012 case LSM9DS1_MAG_LP_1Hz25:
1013 *val = LSM9DS1_MAG_LP_1Hz25;
1014 break;
1015
1016 case LSM9DS1_MAG_LP_2Hz5:
1017 *val = LSM9DS1_MAG_LP_2Hz5;
1018 break;
1019
1020 case LSM9DS1_MAG_LP_5Hz:
1021 *val = LSM9DS1_MAG_LP_5Hz;
1022 break;
1023
1024 case LSM9DS1_MAG_LP_10Hz:
1025 *val = LSM9DS1_MAG_LP_10Hz;
1026 break;
1027
1028 case LSM9DS1_MAG_LP_20Hz:
1029 *val = LSM9DS1_MAG_LP_20Hz;
1030 break;
1031
1032 case LSM9DS1_MAG_LP_40Hz:
1033 *val = LSM9DS1_MAG_LP_40Hz;
1034 break;
1035
1036 case LSM9DS1_MAG_LP_80Hz:
1037 *val = LSM9DS1_MAG_LP_80Hz;
1038 break;
1039
1040 case LSM9DS1_MAG_MP_0Hz625:
1041 *val = LSM9DS1_MAG_MP_0Hz625;
1042 break;
1043
1044 case LSM9DS1_MAG_MP_1Hz25:
1045 *val = LSM9DS1_MAG_MP_1Hz25;
1046 break;
1047
1048 case LSM9DS1_MAG_MP_2Hz5:
1049 *val = LSM9DS1_MAG_MP_2Hz5;
1050 break;
1051
1052 case LSM9DS1_MAG_MP_5Hz:
1053 *val = LSM9DS1_MAG_MP_5Hz;
1054 break;
1055
1056 case LSM9DS1_MAG_MP_10Hz:
1057 *val = LSM9DS1_MAG_MP_10Hz;
1058 break;
1059
1060 case LSM9DS1_MAG_MP_20Hz:
1061 *val = LSM9DS1_MAG_MP_20Hz;
1062 break;
1063
1064 case LSM9DS1_MAG_MP_40Hz:
1065 *val = LSM9DS1_MAG_MP_40Hz;
1066 break;
1067
1068 case LSM9DS1_MAG_MP_80Hz:
1069 *val = LSM9DS1_MAG_MP_80Hz;
1070 break;
1071
1072 case LSM9DS1_MAG_HP_0Hz625:
1073 *val = LSM9DS1_MAG_HP_0Hz625;
1074 break;
1075
1076 case LSM9DS1_MAG_HP_1Hz25:
1077 *val = LSM9DS1_MAG_HP_1Hz25;
1078 break;
1079
1080 case LSM9DS1_MAG_HP_2Hz5:
1081 *val = LSM9DS1_MAG_HP_2Hz5;
1082 break;
1083
1084 case LSM9DS1_MAG_HP_5Hz:
1085 *val = LSM9DS1_MAG_HP_5Hz;
1086 break;
1087
1088 case LSM9DS1_MAG_HP_10Hz:
1089 *val = LSM9DS1_MAG_HP_10Hz;
1090 break;
1091
1092 case LSM9DS1_MAG_HP_20Hz:
1093 *val = LSM9DS1_MAG_HP_20Hz;
1094 break;
1095
1096 case LSM9DS1_MAG_HP_40Hz:
1097 *val = LSM9DS1_MAG_HP_40Hz;
1098 break;
1099
1100 case LSM9DS1_MAG_HP_80Hz:
1101 *val = LSM9DS1_MAG_HP_80Hz;
1102 break;
1103
1104 case LSM9DS1_MAG_UHP_0Hz625:
1105 *val = LSM9DS1_MAG_UHP_0Hz625;
1106 break;
1107
1108 case LSM9DS1_MAG_UHP_1Hz25:
1109 *val = LSM9DS1_MAG_UHP_1Hz25;
1110 break;
1111
1112 case LSM9DS1_MAG_UHP_2Hz5:
1113 *val = LSM9DS1_MAG_UHP_2Hz5;
1114 break;
1115
1116 case LSM9DS1_MAG_UHP_5Hz:
1117 *val = LSM9DS1_MAG_UHP_5Hz;
1118 break;
1119
1120 case LSM9DS1_MAG_UHP_10Hz:
1121 *val = LSM9DS1_MAG_UHP_10Hz;
1122 break;
1123
1124 case LSM9DS1_MAG_UHP_20Hz:
1125 *val = LSM9DS1_MAG_UHP_20Hz;
1126 break;
1127
1128 case LSM9DS1_MAG_UHP_40Hz:
1129 *val = LSM9DS1_MAG_UHP_40Hz;
1130 break;
1131
1132 case LSM9DS1_MAG_UHP_80Hz:
1133 *val = LSM9DS1_MAG_UHP_80Hz;
1134 break;
1135
1136 case LSM9DS1_MAG_UHP_155Hz:
1137 *val = LSM9DS1_MAG_UHP_155Hz;
1138 break;
1139
1140 case LSM9DS1_MAG_HP_300Hz:
1141 *val = LSM9DS1_MAG_HP_300Hz;
1142 break;
1143
1144 case LSM9DS1_MAG_MP_560Hz:
1145 *val = LSM9DS1_MAG_MP_560Hz;
1146 break;
1147
1148 case LSM9DS1_MAG_LP_1000Hz:
1149 *val = LSM9DS1_MAG_LP_1000Hz;
1150 break;
1151
1152 case LSM9DS1_MAG_ONE_SHOT:
1153 *val = LSM9DS1_MAG_ONE_SHOT;
1154 break;
1155
1156 default:
1157 *val = LSM9DS1_MAG_POWER_DOWN;
1158 break;
1159 }
1160
1161 return ret;
1162}
1163
1172int32_t lsm9ds1_mag_full_scale_set(const stmdev_ctx_t *ctx,
1173 lsm9ds1_mag_fs_t val)
1174{
1175 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1176 int32_t ret;
1177
1178 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M,
1179 (uint8_t *)&ctrl_reg2_m, 1);
1180
1181 if (ret == 0)
1182 {
1183 ctrl_reg2_m.fs = (uint8_t)val;
1184 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_M,
1185 (uint8_t *)&ctrl_reg2_m, 1);
1186 }
1187
1188 return ret;
1189}
1190
1199int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx,
1200 lsm9ds1_mag_fs_t *val)
1201{
1202 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1203 int32_t ret;
1204
1205 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_M,
1206 (uint8_t *)&ctrl_reg2_m, 1);
1207
1208 switch (ctrl_reg2_m.fs)
1209 {
1210 case LSM9DS1_4Ga:
1211 *val = LSM9DS1_4Ga;
1212 break;
1213
1214 case LSM9DS1_8Ga:
1215 *val = LSM9DS1_8Ga;
1216 break;
1217
1218 case LSM9DS1_12Ga:
1219 *val = LSM9DS1_12Ga;
1220 break;
1221
1222 case LSM9DS1_16Ga:
1223 *val = LSM9DS1_16Ga;
1224 break;
1225
1226 default:
1227 *val = LSM9DS1_4Ga;
1228 break;
1229 }
1230
1231 return ret;
1232}
1233
1242int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx,
1243 uint8_t *val)
1244{
1245 lsm9ds1_status_reg_m_t status_reg_m;
1246 int32_t ret;
1247
1248 ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG_M,
1249 (uint8_t *)&status_reg_m, 1);
1250 *val = status_reg_m.zyxda;
1251
1252 return ret;
1253}
1254
1276int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1277{
1278 uint8_t buff[2];
1279 int32_t ret;
1280
1281 ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_TEMP_L, buff, 2);
1282 val[0] = (int16_t)buff[1];
1283 val[0] = (val[0] * 256) + (int16_t)buff[0];
1284
1285 return ret;
1286}
1287
1297int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1298{
1299 uint8_t buff[6];
1300 int32_t ret;
1301
1302 ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_G, buff, 6);
1303 val[0] = (int16_t)buff[1];
1304 val[0] = (val[0] * 256) + (int16_t)buff[0];
1305 val[1] = (int16_t)buff[3];
1306 val[1] = (val[1] * 256) + (int16_t)buff[2];
1307 val[2] = (int16_t)buff[5];
1308 val[2] = (val[2] * 256) + (int16_t)buff[4];
1309
1310 return ret;
1311}
1312
1322int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1323{
1324 uint8_t buff[6];
1325 int32_t ret;
1326
1327 ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_XL, buff, 6);
1328 val[0] = (int16_t)buff[1];
1329 val[0] = (val[0] * 256) + (int16_t)buff[0];
1330 val[1] = (int16_t)buff[3];
1331 val[1] = (val[1] * 256) + (int16_t)buff[2];
1332 val[2] = (int16_t)buff[5];
1333 val[2] = (val[2] * 256) + (int16_t)buff[4];
1334
1335 return ret;
1336}
1337
1347int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1348{
1349 uint8_t buff[6];
1350 int32_t ret;
1351
1352 ret = lsm9ds1_read_reg(ctx, LSM9DS1_OUT_X_L_M, buff, 6);
1353 val[0] = (int16_t)buff[1];
1354 val[0] = (val[0] * 256) + (int16_t)buff[0];
1355 val[1] = (int16_t)buff[3];
1356 val[1] = (val[1] * 256) + (int16_t)buff[2];
1357 val[2] = (int16_t)buff[5];
1358 val[2] = (val[2] * 256) + (int16_t)buff[4];
1359
1360 return ret;
1361}
1362
1371int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, uint8_t *val)
1372{
1373 lsm9ds1_int_src_m_t int_src_m;
1374 int32_t ret;
1375
1376 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1);
1377 *val = int_src_m.mroi;
1378
1379 return ret;
1380}
1381
1403int32_t lsm9ds1_dev_id_get(const stmdev_ctx_t *ctx_mag,
1404 stmdev_ctx_t *ctx_imu,
1405 lsm9ds1_id_t *buff)
1406{
1407 int32_t ret;
1408
1409 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_WHO_AM_I,
1410 (uint8_t *) & (buff->imu), 1);
1411
1412 if (ret == 0)
1413 {
1414 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_WHO_AM_I_M,
1415 (uint8_t *) & (buff->mag), 1);
1416 }
1417
1418 return ret;
1419}
1420
1430int32_t lsm9ds1_dev_status_get(const stmdev_ctx_t *ctx_mag,
1431 stmdev_ctx_t *ctx_imu,
1432 lsm9ds1_status_t *val)
1433{
1434 int32_t ret;
1435
1436 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_STATUS_REG,
1437 (uint8_t *) & (val->status_imu), 1);
1438
1439 if (ret == 0)
1440 {
1441 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_STATUS_REG_M,
1442 (uint8_t *) & (val->status_mag), 1);
1443 }
1444
1445 return ret;
1446}
1447
1457int32_t lsm9ds1_dev_reset_set(const stmdev_ctx_t *ctx_mag,
1458 stmdev_ctx_t *ctx_imu,
1459 uint8_t val)
1460{
1461 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1462 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1463 int32_t ret;
1464
1465 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1466 (uint8_t *)&ctrl_reg8, 1);
1467
1468 if (ret == 0)
1469 {
1470 ctrl_reg8.sw_reset = (uint8_t)val;
1471 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1472 (uint8_t *)&ctrl_reg8, 1);
1473 }
1474
1475 if (ret == 0)
1476 {
1477 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1478 (uint8_t *)&ctrl_reg2_m, 1);
1479 }
1480
1481 if (ret == 0)
1482 {
1483 ctrl_reg2_m.soft_rst = (uint8_t)val;
1484 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1485 (uint8_t *)&ctrl_reg2_m, 1);
1486 }
1487
1488 return ret;
1489}
1490
1500int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag,
1501 stmdev_ctx_t *ctx_imu,
1502 uint8_t *val)
1503{
1504 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1505 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1506 int32_t ret;
1507
1508 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1509 (uint8_t *)&ctrl_reg8, 1);
1510
1511 if (ret == 0)
1512 {
1513 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1514 (uint8_t *)&ctrl_reg2_m, 1);
1515 *val = (uint8_t)(ctrl_reg2_m.soft_rst | ctrl_reg8.sw_reset);
1516 }
1517
1518 return ret;
1519}
1520
1530int32_t lsm9ds1_dev_data_format_set(const stmdev_ctx_t *ctx_mag,
1531 stmdev_ctx_t *ctx_imu,
1532 lsm9ds1_ble_t val)
1533{
1534 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1535 lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m;
1536 int32_t ret;
1537
1538 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1539 (uint8_t *)&ctrl_reg8, 1);
1540
1541 if (ret == 0)
1542 {
1543 ctrl_reg8.ble = (uint8_t)val;
1544 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1545 (uint8_t *)&ctrl_reg8, 1);
1546 }
1547
1548 if (ret == 0)
1549 {
1550 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
1551 (uint8_t *)&ctrl_reg4_m, 1);
1552 }
1553
1554 if (ret == 0)
1555 {
1556 ctrl_reg4_m.ble = (uint8_t)val;
1557 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
1558 (uint8_t *)&ctrl_reg4_m, 1);
1559 }
1560
1561 return ret;
1562}
1563
1573int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag,
1574 stmdev_ctx_t *ctx_imu,
1575 lsm9ds1_ble_t *val)
1576{
1577 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1578 lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m;
1579 int32_t ret;
1580
1581 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1582 (uint8_t *)&ctrl_reg8, 1);
1583
1584 if (ret == 0)
1585 {
1586 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG4_M,
1587 (uint8_t *)&ctrl_reg4_m, 1);
1588 }
1589
1590 switch (ctrl_reg8.ble & ctrl_reg4_m.ble)
1591 {
1592 case LSM9DS1_LSB_LOW_ADDRESS:
1593 *val = LSM9DS1_LSB_LOW_ADDRESS;
1594 break;
1595
1596 case LSM9DS1_MSB_LOW_ADDRESS:
1597 *val = LSM9DS1_MSB_LOW_ADDRESS;
1598 break;
1599
1600 default:
1601 *val = LSM9DS1_LSB_LOW_ADDRESS;
1602 break;
1603 }
1604
1605 return ret;
1606}
1607
1617int32_t lsm9ds1_dev_boot_set(const stmdev_ctx_t *ctx_mag,
1618 stmdev_ctx_t *ctx_imu,
1619 uint8_t val)
1620{
1621 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1622 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1623 int32_t ret;
1624
1625 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1626 (uint8_t *)&ctrl_reg8, 1);
1627
1628 if (ret == 0)
1629 {
1630 ctrl_reg8.boot = (uint8_t)val;
1631 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1632 (uint8_t *)&ctrl_reg8, 1);
1633 }
1634
1635 if (ret == 0)
1636 {
1637 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1638 (uint8_t *)&ctrl_reg2_m, 1);
1639 }
1640
1641 if (ret == 0)
1642 {
1643 ctrl_reg2_m.reboot = (uint8_t)val;
1644 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1645 (uint8_t *)&ctrl_reg2_m, 1);
1646 }
1647
1648 return ret;
1649}
1650
1660int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag,
1661 stmdev_ctx_t *ctx_imu,
1662 uint8_t *val)
1663{
1664 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m;
1665 lsm9ds1_ctrl_reg8_t ctrl_reg8;
1666 int32_t ret;
1667
1668 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
1669 (uint8_t *)&ctrl_reg8, 1);
1670
1671 if (ret == 0)
1672 {
1673 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG2_M,
1674 (uint8_t *)&ctrl_reg2_m, 1);
1675 *val = (uint8_t)ctrl_reg2_m.reboot & ctrl_reg8.boot;
1676 }
1677
1678 return ret;
1679}
1680
1702int32_t lsm9ds1_gy_filter_reference_set(const stmdev_ctx_t *ctx,
1703 uint8_t *buff)
1704{
1705 int32_t ret;
1706
1707 ret = lsm9ds1_write_reg(ctx, LSM9DS1_REFERENCE_G, buff, 1);
1708
1709 return ret;
1710}
1711
1720int32_t lsm9ds1_gy_filter_reference_get(const stmdev_ctx_t *ctx,
1721 uint8_t *buff)
1722{
1723 int32_t ret;
1724
1725 ret = lsm9ds1_read_reg(ctx, LSM9DS1_REFERENCE_G, buff, 1);
1726
1727 return ret;
1728}
1729
1738int32_t lsm9ds1_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx,
1739 lsm9ds1_gy_lp_bw_t val)
1740{
1741 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
1742 int32_t ret;
1743
1744 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
1745 (uint8_t *)&ctrl_reg1_g, 1);
1746
1747 if (ret == 0)
1748 {
1749 ctrl_reg1_g.bw_g = (uint8_t)val;
1750 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_G,
1751 (uint8_t *)&ctrl_reg1_g, 1);
1752 }
1753
1754 return ret;
1755}
1756
1765int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx,
1766 lsm9ds1_gy_lp_bw_t *val)
1767{
1768 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g;
1769 int32_t ret;
1770
1771 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_G,
1772 (uint8_t *)&ctrl_reg1_g, 1);
1773
1774 switch (ctrl_reg1_g.bw_g)
1775 {
1776 case LSM9DS1_LP_STRONG:
1777 *val = LSM9DS1_LP_STRONG;
1778 break;
1779
1780 case LSM9DS1_LP_MEDIUM:
1781 *val = LSM9DS1_LP_MEDIUM;
1782 break;
1783
1784 case LSM9DS1_LP_LIGHT:
1785 *val = LSM9DS1_LP_LIGHT;
1786 break;
1787
1788 case LSM9DS1_LP_ULTRA_LIGHT:
1789 *val = LSM9DS1_LP_ULTRA_LIGHT;
1790 break;
1791
1792 default:
1793 *val = LSM9DS1_LP_STRONG;
1794 break;
1795 }
1796
1797 return ret;
1798}
1799
1808int32_t lsm9ds1_gy_filter_out_path_set(const stmdev_ctx_t *ctx,
1809 lsm9ds1_gy_out_path_t val)
1810{
1811 lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g;
1812 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
1813 int32_t ret;
1814
1815 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
1816 (uint8_t *)&ctrl_reg2_g, 1);
1817
1818 if (ret == 0)
1819 {
1820 ctrl_reg2_g.out_sel = ((uint8_t)val & 0x03U);
1821 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_G,
1822 (uint8_t *)&ctrl_reg2_g, 1);
1823 }
1824
1825 if (ret == 0)
1826 {
1827 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
1828 (uint8_t *)&ctrl_reg3_g, 1);
1829 }
1830
1831 if (ret == 0)
1832 {
1833 ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4);
1834 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
1835 (uint8_t *)&ctrl_reg3_g, 1);
1836 }
1837
1838 return ret;
1839}
1840
1849int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx,
1850 lsm9ds1_gy_out_path_t *val)
1851{
1852 lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g;
1853 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
1854 int32_t ret;
1855
1856 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
1857 (uint8_t *)&ctrl_reg2_g, 1);
1858
1859 if (ret == 0)
1860 {
1861 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
1862 (uint8_t *)&ctrl_reg3_g, 1);
1863 }
1864
1865 switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.out_sel)
1866 {
1867 case LSM9DS1_LPF1_OUT:
1868 *val = LSM9DS1_LPF1_OUT;
1869 break;
1870
1871 case LSM9DS1_LPF1_HPF_OUT:
1872 *val = LSM9DS1_LPF1_HPF_OUT;
1873 break;
1874
1875 case LSM9DS1_LPF1_LPF2_OUT:
1876 *val = LSM9DS1_LPF1_LPF2_OUT;
1877 break;
1878
1879 case LSM9DS1_LPF1_HPF_LPF2_OUT:
1880 *val = LSM9DS1_LPF1_HPF_LPF2_OUT;
1881 break;
1882
1883 default:
1884 *val = LSM9DS1_LPF1_OUT;
1885 break;
1886 }
1887
1888 return ret;
1889}
1890
1899int32_t lsm9ds1_gy_filter_int_path_set(const stmdev_ctx_t *ctx,
1900 lsm9ds1_gy_int_path_t val)
1901{
1902 lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g;
1903 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
1904 int32_t ret;
1905
1906 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
1907 (uint8_t *)&ctrl_reg2_g, 1);
1908
1909 if (ret == 0)
1910 {
1911 ctrl_reg2_g.int_sel = ((uint8_t)val & 0x03U);
1912 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG2_G,
1913 (uint8_t *)&ctrl_reg2_g, 1);
1914 }
1915
1916 if (ret == 0)
1917 {
1918 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
1919 (uint8_t *)&ctrl_reg3_g, 1);
1920 }
1921
1922 if (ret == 0)
1923 {
1924 ctrl_reg3_g.hp_en = (((uint8_t)val & 0x10U) >> 4);
1925 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
1926 (uint8_t *)&ctrl_reg3_g, 1);
1927 }
1928
1929 return ret;
1930}
1931
1940int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx,
1941 lsm9ds1_gy_int_path_t *val)
1942{
1943 lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g;
1944 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
1945 int32_t ret;
1946
1947 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG2_G,
1948 (uint8_t *)&ctrl_reg2_g, 1);
1949
1950 if (ret == 0)
1951 {
1952 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
1953 (uint8_t *)&ctrl_reg3_g, 1);
1954 }
1955
1956 switch ((ctrl_reg3_g.hp_en << 4) | ctrl_reg2_g.int_sel)
1957 {
1958 case LSM9DS1_LPF1_INT:
1959 *val = LSM9DS1_LPF1_INT;
1960 break;
1961
1962 case LSM9DS1_LPF1_HPF_INT:
1963 *val = LSM9DS1_LPF1_HPF_INT;
1964 break;
1965
1966 case LSM9DS1_LPF1_LPF2_INT:
1967 *val = LSM9DS1_LPF1_LPF2_INT;
1968 break;
1969
1970 case LSM9DS1_LPF1_HPF_LPF2_INT:
1971 *val = LSM9DS1_LPF1_HPF_LPF2_INT;
1972 break;
1973
1974 default:
1975 *val = LSM9DS1_LPF1_INT;
1976 break;
1977 }
1978
1979 return ret;
1980}
1981
1990int32_t lsm9ds1_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx,
1991 lsm9ds1_gy_hp_bw_t val)
1992{
1993 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
1994 int32_t ret;
1995
1996 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
1997 (uint8_t *)&ctrl_reg3_g, 1);
1998
1999 if (ret == 0)
2000 {
2001 ctrl_reg3_g.hpcf_g = (uint8_t)val;
2002 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG3_G,
2003 (uint8_t *)&ctrl_reg3_g, 1);
2004 }
2005
2006 return ret;
2007}
2008
2017int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx,
2018 lsm9ds1_gy_hp_bw_t *val)
2019{
2020 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g;
2021 int32_t ret;
2022
2023 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG3_G,
2024 (uint8_t *)&ctrl_reg3_g, 1);
2025
2026 switch (ctrl_reg3_g.hpcf_g)
2027 {
2028 case LSM9DS1_HP_EXTREME:
2029 *val = LSM9DS1_HP_EXTREME;
2030 break;
2031
2032 case LSM9DS1_HP_ULTRA_STRONG:
2033 *val = LSM9DS1_HP_ULTRA_STRONG;
2034 break;
2035
2036 case LSM9DS1_HP_STRONG:
2037 *val = LSM9DS1_HP_STRONG;
2038 break;
2039
2040 case LSM9DS1_HP_ULTRA_HIGH:
2041 *val = LSM9DS1_HP_ULTRA_HIGH;
2042 break;
2043
2044 case LSM9DS1_HP_HIGH:
2045 *val = LSM9DS1_HP_HIGH;
2046 break;
2047
2048 case LSM9DS1_HP_MEDIUM:
2049 *val = LSM9DS1_HP_MEDIUM;
2050 break;
2051
2052 case LSM9DS1_HP_LOW:
2053 *val = LSM9DS1_HP_LOW;
2054 break;
2055
2056 case LSM9DS1_HP_ULTRA_LOW:
2057 *val = LSM9DS1_HP_ULTRA_LOW;
2058 break;
2059
2060 case LSM9DS1_HP_LIGHT:
2061 *val = LSM9DS1_HP_LIGHT;
2062 break;
2063
2064 case LSM9DS1_HP_ULTRA_LIGHT:
2065 *val = LSM9DS1_HP_ULTRA_LIGHT;
2066 break;
2067
2068 default:
2069 *val = LSM9DS1_HP_EXTREME;
2070 break;
2071 }
2072
2073 return ret;
2074}
2075
2084int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx,
2085 lsm9ds1_xl_aa_bw_t val)
2086{
2087 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
2088 int32_t ret;
2089
2090 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
2091 (uint8_t *)&ctrl_reg6_xl, 1);
2092
2093 if (ret == 0)
2094 {
2095 ctrl_reg6_xl.bw_xl = ((uint8_t)val & 0x03U);
2096 ctrl_reg6_xl.bw_scal_odr = (((uint8_t)val & 0x10U) >> 4);
2097 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG6_XL,
2098 (uint8_t *)&ctrl_reg6_xl, 1);
2099 }
2100
2101 return ret;
2102}
2103
2112int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx,
2113 lsm9ds1_xl_aa_bw_t *val)
2114{
2115 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl;
2116 int32_t ret;
2117
2118 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG6_XL,
2119 (uint8_t *)&ctrl_reg6_xl, 1);
2120
2121 switch ((ctrl_reg6_xl.bw_scal_odr << 4) | ctrl_reg6_xl.bw_xl)
2122 {
2123 case LSM9DS1_AUTO:
2124 *val = LSM9DS1_AUTO;
2125 break;
2126
2127 case LSM9DS1_408Hz:
2128 *val = LSM9DS1_408Hz;
2129 break;
2130
2131 case LSM9DS1_211Hz:
2132 *val = LSM9DS1_211Hz;
2133 break;
2134
2135 case LSM9DS1_105Hz:
2136 *val = LSM9DS1_105Hz;
2137 break;
2138
2139 case LSM9DS1_50Hz:
2140 *val = LSM9DS1_50Hz;
2141 break;
2142
2143 default:
2144 *val = LSM9DS1_AUTO;
2145 break;
2146 }
2147
2148 return ret;
2149}
2150
2159int32_t lsm9ds1_xl_filter_int_path_set(const stmdev_ctx_t *ctx,
2160 lsm9ds1_xl_hp_path_t val)
2161{
2162 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2163 int32_t ret;
2164
2165 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2166 (uint8_t *)&ctrl_reg7_xl, 1);
2167
2168 if (ret == 0)
2169 {
2170 ctrl_reg7_xl.hpis1 = (uint8_t)val;
2171 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2172 (uint8_t *)&ctrl_reg7_xl, 1);
2173 }
2174
2175 return ret;
2176}
2177
2186int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx,
2187 lsm9ds1_xl_hp_path_t *val)
2188{
2189 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2190 int32_t ret;
2191
2192 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2193 (uint8_t *)&ctrl_reg7_xl, 1);
2194
2195 switch (ctrl_reg7_xl.hpis1)
2196 {
2197 case LSM9DS1_HP_DIS:
2198 *val = LSM9DS1_HP_DIS;
2199 break;
2200
2201 case LSM9DS1_HP_EN:
2202 *val = LSM9DS1_HP_EN;
2203 break;
2204
2205 default:
2206 *val = LSM9DS1_HP_DIS;
2207 break;
2208 }
2209
2210 return ret;
2211}
2212
2221int32_t lsm9ds1_xl_filter_out_path_set(const stmdev_ctx_t *ctx,
2222 lsm9ds1_xl_out_path_t val)
2223{
2224 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2225 int32_t ret;
2226
2227 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2228 (uint8_t *)&ctrl_reg7_xl, 1);
2229
2230 if (ret == 0)
2231 {
2232 ctrl_reg7_xl.fds = (uint8_t)val;
2233 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2234 (uint8_t *)&ctrl_reg7_xl, 1);
2235 }
2236
2237 return ret;
2238}
2239
2248int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx,
2249 lsm9ds1_xl_out_path_t *val)
2250{
2251 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2252 int32_t ret;
2253
2254 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2255 (uint8_t *)&ctrl_reg7_xl, 1);
2256
2257 switch (ctrl_reg7_xl.fds)
2258 {
2259 case LSM9DS1_LP_OUT:
2260 *val = LSM9DS1_LP_OUT;
2261 break;
2262
2263 case LSM9DS1_HP_OUT:
2264 *val = LSM9DS1_HP_OUT;
2265 break;
2266
2267 default:
2268 *val = LSM9DS1_LP_OUT;
2269 break;
2270 }
2271
2272 return ret;
2273}
2274
2284int32_t lsm9ds1_xl_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx,
2285 lsm9ds1_xl_lp_bw_t val)
2286{
2287 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2288 int32_t ret;
2289
2290 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2291 (uint8_t *)&ctrl_reg7_xl, 1);
2292
2293 if (ret == 0)
2294 {
2295 ctrl_reg7_xl.hr = ((uint8_t)val & 0x10U) >> 4;
2296 ctrl_reg7_xl.dcf = ((uint8_t)val & 0x03U);
2297 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2298 (uint8_t *)&ctrl_reg7_xl, 1);
2299 }
2300
2301 return ret;
2302}
2303
2313int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx,
2314 lsm9ds1_xl_lp_bw_t *val)
2315{
2316 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2317 int32_t ret;
2318
2319 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2320 (uint8_t *)&ctrl_reg7_xl, 1);
2321
2322 switch ((ctrl_reg7_xl.hr << 4) + ctrl_reg7_xl.dcf)
2323 {
2324 case LSM9DS1_LP_DISABLE:
2325 *val = LSM9DS1_LP_DISABLE;
2326 break;
2327
2328 case LSM9DS1_LP_ODR_DIV_50:
2329 *val = LSM9DS1_LP_ODR_DIV_50;
2330 break;
2331
2332 case LSM9DS1_LP_ODR_DIV_100:
2333 *val = LSM9DS1_LP_ODR_DIV_100;
2334 break;
2335
2336 case LSM9DS1_LP_ODR_DIV_9:
2337 *val = LSM9DS1_LP_ODR_DIV_9;
2338 break;
2339
2340 case LSM9DS1_LP_ODR_DIV_400:
2341 *val = LSM9DS1_LP_ODR_DIV_400;
2342 break;
2343
2344 default:
2345 *val = LSM9DS1_LP_DISABLE;
2346 break;
2347 }
2348
2349 return ret;
2350}
2351
2361int32_t lsm9ds1_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx,
2362 lsm9ds1_xl_hp_bw_t val)
2363{
2364 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2365 int32_t ret;
2366
2367 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2368 (uint8_t *)&ctrl_reg7_xl, 1);
2369
2370 if (ret == 0)
2371 {
2372 ctrl_reg7_xl.dcf = (uint8_t)val;
2373 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2374 (uint8_t *)&ctrl_reg7_xl, 1);
2375 }
2376
2377 return ret;
2378}
2379
2389int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx,
2390 lsm9ds1_xl_hp_bw_t *val)
2391{
2392 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl;
2393 int32_t ret;
2394
2395 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG7_XL,
2396 (uint8_t *)&ctrl_reg7_xl, 1);
2397
2398 switch (ctrl_reg7_xl.dcf)
2399 {
2400 case LSM9DS1_HP_ODR_DIV_50:
2401 *val = LSM9DS1_HP_ODR_DIV_50;
2402 break;
2403
2404 case LSM9DS1_HP_ODR_DIV_100:
2405 *val = LSM9DS1_HP_ODR_DIV_100;
2406 break;
2407
2408 case LSM9DS1_HP_ODR_DIV_9:
2409 *val = LSM9DS1_HP_ODR_DIV_9;
2410 break;
2411
2412 case LSM9DS1_HP_ODR_DIV_400:
2413 *val = LSM9DS1_HP_ODR_DIV_400;
2414 break;
2415
2416 default:
2417 *val = LSM9DS1_HP_ODR_DIV_50;
2418 break;
2419 }
2420
2421 return ret;
2422}
2423
2432int32_t lsm9ds1_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2433 uint8_t val)
2434{
2435 lsm9ds1_ctrl_reg9_t ctrl_reg9;
2436 int32_t ret;
2437
2438 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
2439
2440 if (ret == 0)
2441 {
2442 ctrl_reg9.drdy_mask_bit = (uint8_t)val;
2443 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
2444 }
2445
2446 return ret;
2447}
2448
2457int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2458 uint8_t *val)
2459{
2460 lsm9ds1_ctrl_reg9_t ctrl_reg9;
2461 int32_t ret;
2462
2463 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
2464 *val = (uint8_t)ctrl_reg9.drdy_mask_bit;
2465
2466 return ret;
2467}
2468
2491int32_t lsm9ds1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2492{
2493 lsm9ds1_ctrl_reg8_t ctrl_reg8;
2494 int32_t ret;
2495
2496 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
2497
2498 if (ret == 0)
2499 {
2500 ctrl_reg8.if_add_inc = (uint8_t)val;
2501 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
2502 }
2503
2504 return ret;
2505}
2506
2516int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2517{
2518 lsm9ds1_ctrl_reg8_t ctrl_reg8;
2519 int32_t ret;
2520
2521 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
2522 *val = (uint8_t)ctrl_reg8.if_add_inc;
2523
2524 return ret;
2525}
2526
2536int32_t lsm9ds1_spi_mode_set(const stmdev_ctx_t *ctx_mag,
2537 stmdev_ctx_t *ctx_imu,
2538 lsm9ds1_sim_t val)
2539{
2540 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
2541 lsm9ds1_ctrl_reg8_t ctrl_reg8;
2542 int32_t ret;
2543
2544 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
2545 (uint8_t *)&ctrl_reg8, 1);
2546
2547 if (ret == 0)
2548 {
2549 ctrl_reg8.sim = (uint8_t)val;
2550 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
2551 (uint8_t *)&ctrl_reg8, 1);
2552 }
2553
2554 if (ret == 0)
2555 {
2556 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2557 (uint8_t *)&ctrl_reg3_m, 1);
2558 }
2559
2560 if (ret == 0)
2561 {
2562 ctrl_reg3_m.sim = (uint8_t)val;
2563 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2564 (uint8_t *)&ctrl_reg3_m, 1);
2565 }
2566
2567 return ret;
2568}
2569
2579int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag,
2580 stmdev_ctx_t *ctx_imu,
2581 lsm9ds1_sim_t *val)
2582{
2583 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
2584 lsm9ds1_ctrl_reg8_t ctrl_reg8;
2585 int32_t ret;
2586
2587 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
2588 (uint8_t *)&ctrl_reg8, 1);
2589
2590 if (ret == 0)
2591 {
2592 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2593 (uint8_t *)&ctrl_reg3_m, 1);
2594 }
2595
2596 switch (ctrl_reg8.sim & ctrl_reg3_m.sim)
2597 {
2598 case LSM9DS1_SPI_4_WIRE:
2599 *val = LSM9DS1_SPI_4_WIRE;
2600 break;
2601
2602 case LSM9DS1_SPI_3_WIRE:
2603 *val = LSM9DS1_SPI_3_WIRE;
2604 break;
2605
2606 default:
2607 *val = LSM9DS1_SPI_4_WIRE;
2608 break;
2609 }
2610
2611 return ret;
2612}
2613
2623int32_t lsm9ds1_i2c_interface_set(const stmdev_ctx_t *ctx_mag,
2624 stmdev_ctx_t *ctx_imu,
2625 lsm9ds1_i2c_dis_t val)
2626{
2627 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
2628 lsm9ds1_ctrl_reg9_t ctrl_reg9;
2629 int32_t ret;
2630
2631 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9,
2632 (uint8_t *)&ctrl_reg9, 1);
2633
2634 if (ret == 0)
2635 {
2636 ctrl_reg9.i2c_disable = (uint8_t)val;
2637 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG9,
2638 (uint8_t *)&ctrl_reg9, 1);
2639 }
2640
2641 if (ret == 0)
2642 {
2643 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2644 (uint8_t *)&ctrl_reg3_m, 1);
2645 }
2646
2647 if (ret == 0)
2648 {
2649 ctrl_reg3_m.i2c_disable = (uint8_t)val;
2650 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2651 (uint8_t *)&ctrl_reg3_m, 1);
2652 }
2653
2654 return ret;
2655}
2656
2666int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag,
2667 stmdev_ctx_t *ctx_imu,
2668 lsm9ds1_i2c_dis_t *val)
2669{
2670 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m;
2671 lsm9ds1_ctrl_reg9_t ctrl_reg9;
2672 int32_t ret;
2673
2674 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG9,
2675 (uint8_t *)&ctrl_reg9, 1);
2676
2677 if (ret == 0)
2678 {
2679 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_CTRL_REG3_M,
2680 (uint8_t *)&ctrl_reg3_m, 1);
2681 }
2682
2683 switch (ctrl_reg9.i2c_disable & ctrl_reg3_m.i2c_disable)
2684 {
2685 case LSM9DS1_I2C_ENABLE:
2686 *val = LSM9DS1_I2C_ENABLE;
2687 break;
2688
2689 case LSM9DS1_I2C_DISABLE:
2690 *val = LSM9DS1_I2C_DISABLE;
2691 break;
2692
2693 default:
2694 *val = LSM9DS1_I2C_ENABLE;
2695 break;
2696 }
2697
2698 return ret;
2699}
2700
2722int32_t lsm9ds1_pin_logic_set(const stmdev_ctx_t *ctx,
2723 lsm9ds1_pin_logic_t val)
2724{
2725 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
2726 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
2727 int32_t ret;
2728
2729 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
2730 (uint8_t *)&int_gen_cfg_xl, 1);
2731
2732 if (ret == 0)
2733 {
2734 int_gen_cfg_xl.aoi_xl = (uint8_t)val;
2735 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
2736 (uint8_t *)&int_gen_cfg_xl, 1);
2737 }
2738
2739 if (ret == 0)
2740 {
2741 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
2742 (uint8_t *)&int_gen_cfg_g, 1);
2743 }
2744
2745 if (ret == 0)
2746 {
2747 int_gen_cfg_g.aoi_g = (uint8_t)val;
2748 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
2749 (uint8_t *)&int_gen_cfg_g, 1);
2750 }
2751
2752 return ret;
2753}
2754
2763int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx,
2764 lsm9ds1_pin_logic_t *val)
2765{
2766 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
2767 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
2768 int32_t ret;
2769
2770 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
2771 (uint8_t *)&int_gen_cfg_xl, 1);
2772
2773 if (ret == 0)
2774 {
2775 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
2776 (uint8_t *)&int_gen_cfg_g, 1);
2777 }
2778
2779 switch (int_gen_cfg_xl.aoi_xl & int_gen_cfg_g.aoi_g)
2780 {
2781 case LSM9DS1_LOGIC_OR:
2782 *val = LSM9DS1_LOGIC_OR;
2783 break;
2784
2785 case LSM9DS1_LOGIC_AND:
2786 *val = LSM9DS1_LOGIC_AND;
2787 break;
2788
2789 default:
2790 *val = LSM9DS1_LOGIC_OR;
2791 break;
2792 }
2793
2794 return ret;
2795}
2796
2805int32_t lsm9ds1_pin_int1_route_set(const stmdev_ctx_t *ctx,
2806 lsm9ds1_pin_int1_route_t val)
2807{
2808 lsm9ds1_int1_ctrl_t int1_ctrl;
2809 int32_t ret;
2810
2811 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2812
2813 if (ret == 0)
2814 {
2815 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
2816 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
2817 int1_ctrl.int1_boot = val.int1_boot;
2818 int1_ctrl.int1_fth = val.int1_fth;
2819 int1_ctrl.int1_ovr = val.int1_ovr;
2820 int1_ctrl.int1_fss5 = val.int1_fss5;
2821 int1_ctrl.int1_ig_xl = val.int1_ig_xl;
2822 int1_ctrl.int1_ig_g = val.int1_ig_g;
2823 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2824 }
2825
2826 return ret;
2827}
2828
2837int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx,
2838 lsm9ds1_pin_int1_route_t *val)
2839{
2840 lsm9ds1_int1_ctrl_t int1_ctrl;
2841 int32_t ret;
2842
2843 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2844 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
2845 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
2846 val->int1_boot = int1_ctrl.int1_boot;
2847 val->int1_fth = int1_ctrl.int1_fth;
2848 val->int1_ovr = int1_ctrl.int1_ovr;
2849 val->int1_fss5 = int1_ctrl.int1_fss5;
2850 val->int1_ig_xl = int1_ctrl.int1_ig_xl;
2851 val->int1_ig_g = int1_ctrl.int1_ig_g;
2852
2853 return ret;
2854}
2855
2864int32_t lsm9ds1_pin_int2_route_set(const stmdev_ctx_t *ctx,
2865 lsm9ds1_pin_int2_route_t val)
2866{
2867 lsm9ds1_int2_ctrl_t int2_ctrl;
2868 int32_t ret;
2869
2870 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2871
2872 if (ret == 0)
2873 {
2874 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
2875 int2_ctrl.int2_inact = val.int2_inact;
2876 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
2877 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
2878 int2_ctrl.int2_fth = val.int2_fth;
2879 int2_ctrl.int2_ovr = val.int2_ovr;
2880 int2_ctrl.int2_fss5 = val.int2_fss5;
2881 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2882 }
2883
2884 return ret;
2885}
2886
2895int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx,
2896 lsm9ds1_pin_int2_route_t *val)
2897{
2898 lsm9ds1_int2_ctrl_t int2_ctrl;
2899 int32_t ret;
2900
2901 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2902 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
2903 val->int2_inact = int2_ctrl.int2_inact;
2904 val->int2_fss5 = int2_ctrl.int2_fss5;
2905 val->int2_ovr = int2_ctrl.int2_ovr;
2906 val->int2_fth = int2_ctrl.int2_fth;
2907 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
2908 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
2909
2910 return ret;
2911}
2912
2922int32_t lsm9ds1_pin_notification_set(const stmdev_ctx_t *ctx_mag,
2923 stmdev_ctx_t *ctx_imu,
2924 lsm9ds1_lir_t val)
2925{
2926 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
2927 lsm9ds1_int_cfg_m_t int_cfg_m;
2928 lsm9ds1_ctrl_reg4_t ctrl_reg4;
2929 int32_t ret;
2930
2931 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG4,
2932 (uint8_t *)&ctrl_reg4, 1);
2933
2934 if (ret == 0)
2935 {
2936 ctrl_reg4.lir_xl1 = (uint8_t)val;
2937 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG4,
2938 (uint8_t *)&ctrl_reg4, 1);
2939 }
2940
2941 if (ret == 0)
2942 {
2943 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
2944 (uint8_t *)&int_gen_cfg_g, 1);
2945 }
2946
2947 if (ret == 0)
2948 {
2949 int_gen_cfg_g.lir_g = (uint8_t)val;
2950 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
2951 (uint8_t *)&int_gen_cfg_g, 1);
2952 }
2953
2954 if (ret == 0)
2955 {
2956 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
2957 (uint8_t *)&int_cfg_m, 1);
2958 }
2959
2960 if (ret == 0)
2961 {
2962 int_cfg_m.iel = (uint8_t)~(uint32_t)val;
2963 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_INT_CFG_M,
2964 (uint8_t *)&int_cfg_m, 1);
2965 }
2966
2967 return ret;
2968}
2969
2979int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag,
2980 stmdev_ctx_t *ctx_imu,
2981 lsm9ds1_lir_t *val)
2982{
2983 lsm9ds1_int_cfg_m_t int_cfg_m;
2984 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
2985 lsm9ds1_ctrl_reg4_t ctrl_reg4;
2986 int32_t ret;
2987
2988 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG4,
2989 (uint8_t *)&ctrl_reg4, 1);
2990
2991 if (ret == 0)
2992 {
2993 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_INT_GEN_CFG_G,
2994 (uint8_t *)&int_gen_cfg_g, 1);
2995 }
2996
2997 if (ret == 0)
2998 {
2999 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
3000 (uint8_t *)&int_cfg_m, 1);
3001 }
3002
3003 switch ((uint8_t)((uint8_t)(~(uint32_t)int_cfg_m.iel) & int_gen_cfg_g.lir_g) & ctrl_reg4.lir_xl1)
3004 {
3005 case LSM9DS1_INT_LATCHED:
3006 *val = LSM9DS1_INT_LATCHED;
3007 break;
3008
3009 case LSM9DS1_INT_PULSED:
3010 *val = LSM9DS1_INT_PULSED;
3011 break;
3012
3013 default:
3014 *val = LSM9DS1_INT_LATCHED;
3015 break;
3016 }
3017
3018 return ret;
3019}
3028int32_t lsm9ds1_pin_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val)
3029{
3030 lsm9ds1_ctrl_reg8_t ctrl_reg8;
3031 int32_t ret;
3032
3033 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
3034
3035 if (ret == 0)
3036 {
3037 ctrl_reg8.pp_od = (uint8_t)val;
3038 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
3039 }
3040
3041 return ret;
3042}
3043
3052int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val)
3053{
3054 lsm9ds1_ctrl_reg8_t ctrl_reg8;
3055 int32_t ret;
3056
3057 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG8, (uint8_t *)&ctrl_reg8, 1);
3058
3059 switch (ctrl_reg8.pp_od)
3060 {
3061 case LSM9DS1_PUSH_PULL:
3062 *val = LSM9DS1_PUSH_PULL;
3063 break;
3064
3065 case LSM9DS1_OPEN_DRAIN:
3066 *val = LSM9DS1_OPEN_DRAIN;
3067 break;
3068
3069 default:
3070 *val = LSM9DS1_PUSH_PULL;
3071 break;
3072 }
3073
3074 return ret;
3075}
3076
3085int32_t lsm9ds1_pin_int_m_route_set(const stmdev_ctx_t *ctx,
3086 lsm9ds1_pin_m_route_t val)
3087{
3088 lsm9ds1_int_cfg_m_t int_cfg_m;
3089 int32_t ret;
3090
3091 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3092
3093 if (ret == 0)
3094 {
3095 int_cfg_m.ien = val.ien;
3096 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3097 }
3098
3099 return ret;
3100}
3101
3110int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx,
3111 lsm9ds1_pin_m_route_t *val)
3112{
3113 lsm9ds1_int_cfg_m_t int_cfg_m;
3114 int32_t ret;
3115
3116 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3117 val->ien = int_cfg_m.ien;
3118
3119 return ret;
3120}
3121
3131int32_t lsm9ds1_pin_polarity_set(const stmdev_ctx_t *ctx_mag,
3132 stmdev_ctx_t *ctx_imu,
3133 lsm9ds1_polarity_t val)
3134{
3135 lsm9ds1_int_cfg_m_t int_cfg_m;
3136 lsm9ds1_ctrl_reg8_t ctrl_reg8;
3137 int32_t ret;
3138
3139 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
3140 (uint8_t *)&int_cfg_m, 1);
3141
3142 if (ret == 0)
3143 {
3144 int_cfg_m.iea = (uint8_t)val;
3145 ret = lsm9ds1_write_reg(ctx_mag, LSM9DS1_INT_CFG_M,
3146 (uint8_t *)&int_cfg_m, 1);
3147 }
3148
3149 if (ret == 0)
3150 {
3151 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
3152 (uint8_t *)&ctrl_reg8, 1);
3153 }
3154
3155 if (ret == 0)
3156 {
3157 ctrl_reg8.h_lactive = (uint8_t)~(uint32_t)val;
3158 ret = lsm9ds1_write_reg(ctx_imu, LSM9DS1_CTRL_REG8,
3159 (uint8_t *)&ctrl_reg8, 1);
3160 }
3161
3162 return ret;
3163}
3164
3174int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag,
3175 stmdev_ctx_t *ctx_imu,
3176 lsm9ds1_polarity_t *val)
3177{
3178 lsm9ds1_int_cfg_m_t int_cfg_m;
3179 lsm9ds1_ctrl_reg8_t ctrl_reg8;
3180 int32_t ret;
3181
3182 ret = lsm9ds1_read_reg(ctx_mag, LSM9DS1_INT_CFG_M,
3183 (uint8_t *)&int_cfg_m, 1);
3184
3185 if (ret == 0)
3186 {
3187 ret = lsm9ds1_read_reg(ctx_imu, LSM9DS1_CTRL_REG8,
3188 (uint8_t *)&ctrl_reg8, 1);
3189 }
3190
3191 switch ((uint8_t)(int_cfg_m.iea & (uint8_t)(~(uint32_t)ctrl_reg8.h_lactive)))
3192 {
3193 case LSM9DS1_ACTIVE_LOW:
3194 *val = LSM9DS1_ACTIVE_LOW;
3195 break;
3196
3197 case LSM9DS1_ACTIVE_HIGH:
3198 *val = LSM9DS1_ACTIVE_HIGH;
3199 break;
3200
3201 default:
3202 *val = LSM9DS1_ACTIVE_LOW;
3203 break;
3204 }
3205
3206 return ret;
3207}
3208
3231int32_t lsm9ds1_xl_trshld_axis_set(const stmdev_ctx_t *ctx,
3232 lsm9ds1_xl_trshld_en_t val)
3233{
3234 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
3235 int32_t ret;
3236
3237 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
3238 (uint8_t *)&int_gen_cfg_xl, 1);
3239
3240 if (ret == 0)
3241 {
3242 int_gen_cfg_xl.xlie_xl = val.xlie_xl;
3243 int_gen_cfg_xl.xhie_xl = val.xhie_xl;
3244 int_gen_cfg_xl.ylie_xl = val.ylie_xl;
3245 int_gen_cfg_xl.zhie_xl = val.zhie_xl;
3246 int_gen_cfg_xl.yhie_xl = val.yhie_xl;
3247 int_gen_cfg_xl.zlie_xl = val.zlie_xl;
3248 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
3249 (uint8_t *)&int_gen_cfg_xl, 1);
3250 }
3251
3252 return ret;
3253}
3254
3264int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx,
3265 lsm9ds1_xl_trshld_en_t *val)
3266{
3267 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
3268 int32_t ret;
3269
3270 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
3271 (uint8_t *)&int_gen_cfg_xl, 1);
3272 val->xlie_xl = int_gen_cfg_xl.xlie_xl;
3273 val->xhie_xl = int_gen_cfg_xl.xhie_xl;
3274 val->ylie_xl = int_gen_cfg_xl.ylie_xl;
3275 val->yhie_xl = int_gen_cfg_xl.yhie_xl;
3276 val->zlie_xl = int_gen_cfg_xl.zlie_xl;
3277 val->zhie_xl = int_gen_cfg_xl.zhie_xl;
3278
3279 return ret;
3280}
3281
3290int32_t lsm9ds1_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t *buff)
3291{
3292 int32_t ret;
3293
3294 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
3295
3296 return ret;
3297}
3298
3307int32_t lsm9ds1_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *buff)
3308{
3309 int32_t ret;
3310
3311 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
3312
3313 return ret;
3314}
3315
3324int32_t lsm9ds1_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx,
3325 uint8_t val)
3326{
3327 lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl;
3328 int32_t ret;
3329
3330 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
3331 (uint8_t *)&int_gen_dur_xl, 1);
3332
3333 if (ret == 0)
3334 {
3335 int_gen_dur_xl.dur_xl = (uint8_t)val;
3336
3337 if (val != 0x00U)
3338 {
3339 int_gen_dur_xl.wait_xl = PROPERTY_ENABLE;
3340 }
3341
3342 else
3343 {
3344 int_gen_dur_xl.wait_xl = PROPERTY_DISABLE;
3345 }
3346
3347 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
3348 (uint8_t *)&int_gen_dur_xl, 1);
3349 }
3350
3351 return ret;
3352}
3353
3362int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx,
3363 uint8_t *val)
3364{
3365 lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl;
3366 int32_t ret;
3367
3368 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_XL,
3369 (uint8_t *)&int_gen_dur_xl, 1);
3370 *val = (uint8_t)int_gen_dur_xl.dur_xl;
3371
3372 return ret;
3373}
3374
3383int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx,
3384 lsm9ds1_gy_trshld_src_t *val)
3385{
3386 lsm9ds1_int_gen_src_g_t int_gen_src_g;
3387 int32_t ret;
3388
3389 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_G,
3390 (uint8_t *)&int_gen_src_g, 1);
3391 val->xl_g = int_gen_src_g.xl_g;
3392 val->xh_g = int_gen_src_g.xh_g;
3393 val->yl_g = int_gen_src_g.yl_g;
3394 val->yh_g = int_gen_src_g.yh_g;
3395 val->zl_g = int_gen_src_g.zl_g;
3396 val->zh_g = int_gen_src_g.zh_g;
3397 val->ia_g = int_gen_src_g.ia_g;
3398
3399 return ret;
3400}
3401
3410int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx,
3411 lsm9ds1_xl_trshld_src_t *val)
3412{
3413 lsm9ds1_int_gen_src_xl_t int_gen_src_xl;
3414 int32_t ret;
3415
3416 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL,
3417 (uint8_t *)&int_gen_src_xl, 1);
3418 val->xl_xl = int_gen_src_xl.xl_xl;
3419 val->xh_xl = int_gen_src_xl.xh_xl;
3420 val->yl_xl = int_gen_src_xl.yl_xl;
3421 val->yh_xl = int_gen_src_xl.yh_xl;
3422 val->zl_xl = int_gen_src_xl.zl_xl;
3423 val->zh_xl = int_gen_src_xl.zh_xl;
3424 val->ia_xl = int_gen_src_xl.ia_xl;
3425
3426 return ret;
3427}
3428
3438int32_t lsm9ds1_gy_trshld_axis_set(const stmdev_ctx_t *ctx,
3439 lsm9ds1_gy_trshld_en_t val)
3440{
3441 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
3442 int32_t ret;
3443
3444 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
3445 (uint8_t *)&int_gen_cfg_g, 1);
3446
3447 if (ret == 0)
3448 {
3449 int_gen_cfg_g.xlie_g = val.xlie_g;
3450 int_gen_cfg_g.xhie_g = val.xhie_g;
3451 int_gen_cfg_g.ylie_g = val.ylie_g;
3452 int_gen_cfg_g.yhie_g = val.yhie_g;
3453 int_gen_cfg_g.zlie_g = val.zlie_g;
3454 int_gen_cfg_g.zhie_g = val.zhie_g;
3455 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
3456 (uint8_t *)&int_gen_cfg_g, 1);
3457 }
3458
3459 return ret;
3460}
3461
3471int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx,
3472 lsm9ds1_gy_trshld_en_t *val)
3473{
3474 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g;
3475 int32_t ret;
3476
3477 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_G,
3478 (uint8_t *)&int_gen_cfg_g, 1);
3479 val->xlie_g = int_gen_cfg_g.xlie_g;
3480 val->xhie_g = int_gen_cfg_g.xhie_g;
3481 val->ylie_g = int_gen_cfg_g.ylie_g;
3482 val->yhie_g = int_gen_cfg_g.yhie_g;
3483 val->zlie_g = int_gen_cfg_g.zlie_g;
3484 val->zhie_g = int_gen_cfg_g.zhie_g;
3485
3486 return ret;
3487}
3488
3497int32_t lsm9ds1_gy_trshld_mode_set(const stmdev_ctx_t *ctx,
3498 lsm9ds1_dcrm_g_t val)
3499{
3500 lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
3501 int32_t ret;
3502
3503 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3504 (uint8_t *)&int_gen_ths_xh_g, 1);
3505
3506 if (ret == 0)
3507 {
3508 int_gen_ths_xh_g.dcrm_g = (uint8_t)val;
3509 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3510 (uint8_t *)&int_gen_ths_xh_g, 1);
3511 }
3512
3513 return ret;
3514}
3515
3524int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx,
3525 lsm9ds1_dcrm_g_t *val)
3526{
3527 lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
3528 int32_t ret;
3529
3530 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3531 (uint8_t *)&int_gen_ths_xh_g, 1);
3532
3533 switch (int_gen_ths_xh_g.dcrm_g)
3534 {
3535 case LSM9DS1_RESET_MODE:
3536 *val = LSM9DS1_RESET_MODE;
3537 break;
3538
3539 case LSM9DS1_DECREMENT_MODE:
3540 *val = LSM9DS1_DECREMENT_MODE;
3541 break;
3542
3543 default:
3544 *val = LSM9DS1_RESET_MODE;
3545 break;
3546 }
3547
3548 return ret;
3549}
3550
3559int32_t lsm9ds1_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val)
3560{
3561 lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
3562 lsm9ds1_int_gen_ths_xl_g_t int_gen_ths_xl_g;
3563 int32_t ret;
3564
3565 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3566 (uint8_t *)&int_gen_ths_xh_g, 1);
3567
3568 if (ret == 0)
3569 {
3570 int_gen_ths_xh_g.ths_g_x = (uint8_t)((val & 0x7F00U) >> 8);
3571 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3572 (uint8_t *)&int_gen_ths_xh_g, 1);
3573 }
3574
3575 if (ret == 0)
3576 {
3577 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
3578 (uint8_t *)&int_gen_ths_xl_g, 1);
3579 }
3580
3581 if (ret == 0)
3582 {
3583 int_gen_ths_xl_g.ths_g_x = (uint8_t)(val & 0x00FFU);
3584 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
3585 (uint8_t *)&int_gen_ths_xl_g, 1);
3586 }
3587
3588 return ret;
3589}
3590
3599int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val)
3600{
3601 lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g;
3602 lsm9ds1_int_gen_ths_xl_g_t int_gen_ths_xl_g;
3603 int32_t ret;
3604
3605 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XH_G,
3606 (uint8_t *)&int_gen_ths_xh_g, 1);
3607
3608 if (ret == 0)
3609 {
3610 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_XL_G,
3611 (uint8_t *)&int_gen_ths_xl_g, 1);
3612 }
3613
3614 *val = int_gen_ths_xh_g.ths_g_x;
3615 *val = *val << 8;
3616 *val += int_gen_ths_xl_g.ths_g_x;
3617
3618 return ret;
3619}
3620
3621
3630int32_t lsm9ds1_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val)
3631{
3632 lsm9ds1_int_gen_ths_yh_g_t int_gen_ths_yh_g;
3633 lsm9ds1_int_gen_ths_yl_g_t int_gen_ths_yl_g;
3634 int32_t ret;
3635
3636 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
3637 (uint8_t *)&int_gen_ths_yh_g, 1);
3638
3639 if (ret == 0)
3640 {
3641 int_gen_ths_yh_g.ths_g_y = (uint8_t)((val & 0x7F00U) >> 8);
3642 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
3643 (uint8_t *)&int_gen_ths_yh_g, 1);
3644 }
3645
3646 if (ret == 0)
3647 {
3648 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
3649 (uint8_t *)&int_gen_ths_yl_g, 1);
3650 }
3651
3652 if (ret == 0)
3653 {
3654 int_gen_ths_yl_g.ths_g_y = (uint8_t)(val & 0x00FFU);
3655 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
3656 (uint8_t *)&int_gen_ths_yl_g, 1);
3657 }
3658
3659 return ret;
3660}
3661
3670int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val)
3671{
3672 lsm9ds1_int_gen_ths_yh_g_t int_gen_ths_yh_g;
3673 lsm9ds1_int_gen_ths_yl_g_t int_gen_ths_yl_g;
3674 int32_t ret;
3675
3676 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YH_G,
3677 (uint8_t *)&int_gen_ths_yh_g, 1);
3678
3679 if (ret == 0)
3680 {
3681 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_YL_G,
3682 (uint8_t *)&int_gen_ths_yl_g, 1);
3683 }
3684
3685 *val = (uint8_t)int_gen_ths_yh_g.ths_g_y;
3686 *val = *val << 8;
3687 *val += int_gen_ths_yl_g.ths_g_y;
3688
3689 return ret;
3690}
3691
3700int32_t lsm9ds1_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val)
3701{
3702 lsm9ds1_int_gen_ths_zh_g_t int_gen_ths_zh_g;
3703 lsm9ds1_int_gen_ths_zl_g_t int_gen_ths_zl_g;
3704 int32_t ret;
3705
3706 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
3707 (uint8_t *)&int_gen_ths_zh_g, 1);
3708
3709 if (ret == 0)
3710 {
3711 int_gen_ths_zh_g.ths_g_z = (uint8_t)((val & 0x7F00U) >> 8);
3712 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
3713 (uint8_t *)&int_gen_ths_zh_g, 1);
3714 }
3715
3716 if (ret == 0)
3717 {
3718 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
3719 (uint8_t *)&int_gen_ths_zl_g, 1);
3720 }
3721
3722 if (ret == 0)
3723 {
3724 int_gen_ths_zl_g.ths_g_z = (uint8_t)(val & 0x00FFU);
3725 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
3726 (uint8_t *)&int_gen_ths_zl_g, 1);
3727 }
3728
3729 return ret;
3730}
3731
3740int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val)
3741{
3742 lsm9ds1_int_gen_ths_zh_g_t int_gen_ths_zh_g;
3743 lsm9ds1_int_gen_ths_zl_g_t int_gen_ths_zl_g;
3744 int32_t ret;
3745
3746 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZH_G,
3747 (uint8_t *)&int_gen_ths_zh_g, 1);
3748
3749 if (ret == 0)
3750 {
3751 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_ZL_G,
3752 (uint8_t *)&int_gen_ths_zl_g, 1);
3753 }
3754
3755 *val = int_gen_ths_zh_g.ths_g_z;
3756 *val = *val << 8;
3757 *val += int_gen_ths_zl_g.ths_g_z;
3758
3759 return ret;
3760}
3761
3770int32_t lsm9ds1_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx,
3771 uint8_t val)
3772{
3773 lsm9ds1_int_gen_dur_g_t int_gen_dur_g;
3774 int32_t ret;
3775
3776 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
3777 (uint8_t *)&int_gen_dur_g, 1);
3778
3779 if (ret == 0)
3780 {
3781 if (val != 0x00U)
3782 {
3783 int_gen_dur_g.wait_g = PROPERTY_ENABLE;
3784 }
3785
3786 else
3787 {
3788 int_gen_dur_g.wait_g = PROPERTY_DISABLE;
3789 }
3790
3791 int_gen_dur_g.dur_g = (uint8_t)val;
3792 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
3793 (uint8_t *)&int_gen_dur_g, 1);
3794 }
3795
3796 return ret;
3797}
3798
3807int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx,
3808 uint8_t *val)
3809{
3810 lsm9ds1_int_gen_dur_g_t int_gen_dur_g;
3811 int32_t ret;
3812
3813 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_DUR_G,
3814 (uint8_t *)&int_gen_dur_g, 1);
3815 *val = (uint8_t)int_gen_dur_g.dur_g;
3816
3817 return ret;
3818}
3819
3828int32_t lsm9ds1_mag_trshld_axis_set(const stmdev_ctx_t *ctx,
3829 lsm9ds1_mag_trshld_axis_t val)
3830{
3831 lsm9ds1_int_cfg_m_t int_cfg_m;
3832 int32_t ret;
3833
3834 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3835
3836 if (ret == 0)
3837 {
3838 int_cfg_m.zien = val.zien;
3839 int_cfg_m.xien = val.xien;
3840 int_cfg_m.yien = val.yien;
3841 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3842 }
3843
3844 return ret;
3845}
3846
3855int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx,
3856 lsm9ds1_mag_trshld_axis_t *val)
3857{
3858 lsm9ds1_int_cfg_m_t int_cfg_m;
3859 int32_t ret;
3860
3861 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_CFG_M, (uint8_t *)&int_cfg_m, 1);
3862 val->zien = int_cfg_m.zien;
3863 val->yien = int_cfg_m.yien;
3864 val->xien = int_cfg_m.xien;
3865
3866 return ret;
3867}
3868
3877int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx,
3878 lsm9ds1_mag_trshld_src_t *val)
3879{
3880 lsm9ds1_int_src_m_t int_src_m;
3881 int32_t ret;
3882
3883 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_SRC_M, (uint8_t *)&int_src_m, 1);
3884 val->_int = int_src_m._int;
3885 val->nth_z = int_src_m.nth_z;
3886 val->nth_y = int_src_m.nth_y;
3887 val->nth_x = int_src_m.nth_x;
3888 val->pth_z = int_src_m.pth_z;
3889 val->pth_y = int_src_m.pth_y;
3890 val->pth_x = int_src_m.pth_x;
3891
3892 return ret;
3893}
3894
3903int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val)
3904{
3905 lsm9ds1_int_ths_l_m_t int_ths_l_m;
3906 lsm9ds1_int_ths_h_m_t int_ths_h_m;
3907 int32_t ret;
3908
3909 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_L_M,
3910 (uint8_t *)&int_ths_l_m, 1);
3911
3912 if (ret == 0)
3913 {
3914 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_THS_H_M,
3915 (uint8_t *)&int_ths_h_m, 1);
3916 }
3917
3918 *val = int_ths_h_m.ths;
3919 *val = *val << 8;
3920 *val += int_ths_l_m.ths;
3921
3922 return ret;
3923}
3924
3946int32_t lsm9ds1_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3947{
3948 lsm9ds1_act_ths_t act_ths;
3949 int32_t ret;
3950
3951 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
3952
3953 if (ret == 0)
3954 {
3955 act_ths.act_ths = (uint8_t)val;
3956 ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
3957 }
3958
3959 return ret;
3960}
3961
3970int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3971{
3972 lsm9ds1_act_ths_t act_ths;
3973 int32_t ret;
3974
3975 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
3976 *val = (uint8_t)act_ths.act_ths;
3977
3978 return ret;
3979}
3980
3989int32_t lsm9ds1_act_mode_set(const stmdev_ctx_t *ctx,
3990 lsm9ds1_act_mode_t val)
3991{
3992 lsm9ds1_act_ths_t act_ths;
3993 lsm9ds1_ctrl_reg9_t ctrl_reg9;
3994 int32_t ret;
3995
3996 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
3997
3998 if (ret == 0)
3999 {
4000 act_ths.sleep_on_inact_en = (uint8_t)val;
4001 ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
4002 }
4003
4004 if (ret == 0)
4005 {
4006 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4007 }
4008
4009 if (ret == 0)
4010 {
4011 ctrl_reg9.sleep_g = (uint8_t)val;
4012 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4013 }
4014
4015 return ret;
4016}
4017
4026int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx,
4027 lsm9ds1_act_mode_t *val)
4028{
4029 lsm9ds1_act_ths_t act_ths;
4030 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4031 int32_t ret;
4032
4033 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_THS, (uint8_t *)&act_ths, 1);
4034
4035 if (ret == 0)
4036 {
4037 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4038 }
4039
4040 switch (act_ths.sleep_on_inact_en & ctrl_reg9.sleep_g)
4041 {
4042 case LSM9DS1_GYRO_POWER_DOWN:
4043 *val = LSM9DS1_GYRO_POWER_DOWN;
4044 break;
4045
4046 case LSM9DS1_GYRO_SLEEP:
4047 *val = LSM9DS1_GYRO_SLEEP;
4048 break;
4049
4050 default:
4051 *val = LSM9DS1_GYRO_POWER_DOWN;
4052 break;
4053 }
4054
4055 return ret;
4056}
4057
4066int32_t lsm9ds1_act_duration_set(const stmdev_ctx_t *ctx, uint8_t *buff)
4067{
4068 int32_t ret;
4069
4070 ret = lsm9ds1_write_reg(ctx, LSM9DS1_ACT_DUR, buff, 1);
4071
4072 return ret;
4073}
4074
4083int32_t lsm9ds1_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *buff)
4084{
4085 int32_t ret;
4086
4087 ret = lsm9ds1_read_reg(ctx, LSM9DS1_ACT_DUR, buff, 1);
4088
4089 return ret;
4090}
4091
4100int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val)
4101{
4102 lsm9ds1_status_reg_t status_reg;
4103 int32_t ret;
4104
4105 ret = lsm9ds1_read_reg(ctx, LSM9DS1_STATUS_REG,
4106 (uint8_t *)&status_reg, 1);
4107
4108 switch (status_reg.inact)
4109 {
4110 case LSM9DS1_ACTIVITY:
4111 *val = LSM9DS1_ACTIVITY;
4112 break;
4113
4114 case LSM9DS1_INACTIVITY:
4115 *val = LSM9DS1_INACTIVITY;
4116 break;
4117
4118 default:
4119 *val = LSM9DS1_ACTIVITY;
4120 break;
4121 }
4122
4123 return ret;
4124}
4125
4147int32_t lsm9ds1_6d_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val)
4148{
4149 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
4150 lsm9ds1_ctrl_reg4_t ctrl_reg4;
4151 int32_t ret;
4152
4153 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
4154 (uint8_t *)&int_gen_cfg_xl, 1);
4155
4156 if (ret == 0)
4157 {
4158 int_gen_cfg_xl._6d = ((uint8_t)val & 0x01U);
4159 int_gen_cfg_xl.aoi_xl = (((uint8_t)val & 0x02U) >> 1);
4160 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
4161 (uint8_t *)&int_gen_cfg_xl, 1);
4162 }
4163
4164 if (ret == 0)
4165 {
4166 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4,
4167 (uint8_t *)&ctrl_reg4, 1);
4168 }
4169
4170 if (ret == 0)
4171 {
4172 ctrl_reg4._4d_xl1 = (((uint8_t)val & 0x04U) >> 2);
4173 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG4,
4174 (uint8_t *)&ctrl_reg4, 1);
4175 }
4176
4177 return ret;
4178}
4179
4188int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val)
4189{
4190 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl;
4191 lsm9ds1_ctrl_reg4_t ctrl_reg4;
4192 int32_t ret;
4193
4194 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_CFG_XL,
4195 (uint8_t *)&int_gen_cfg_xl, 1);
4196
4197 if (ret == 0)
4198 {
4199 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG4,
4200 (uint8_t *)&ctrl_reg4, 1);
4201 }
4202
4203 switch ((ctrl_reg4._4d_xl1 << 2) | (int_gen_cfg_xl.aoi_xl << 1)
4204 | int_gen_cfg_xl.aoi_xl)
4205 {
4206 case LSM9DS1_POS_MOVE_RECO_DISABLE:
4207 *val = LSM9DS1_POS_MOVE_RECO_DISABLE;
4208 break;
4209
4210 case LSM9DS1_6D_MOVE_RECO:
4211 *val = LSM9DS1_6D_MOVE_RECO;
4212 break;
4213
4214 case LSM9DS1_4D_MOVE_RECO:
4215 *val = LSM9DS1_4D_MOVE_RECO;
4216 break;
4217
4218 case LSM9DS1_6D_POS_RECO:
4219 *val = LSM9DS1_6D_POS_RECO;
4220 break;
4221
4222 case LSM9DS1_4D_POS_RECO:
4223 *val = LSM9DS1_4D_POS_RECO;
4224 break;
4225
4226 default:
4227 *val = LSM9DS1_POS_MOVE_RECO_DISABLE;
4228 break;
4229 }
4230
4231 return ret;
4232}
4233
4242int32_t lsm9ds1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff)
4243{
4244 int32_t ret;
4245
4246 ret = lsm9ds1_write_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
4247
4248 return ret;
4249}
4250
4259int32_t lsm9ds1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff)
4260{
4261 int32_t ret;
4262
4263 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_THS_X_XL, buff, 3);
4264
4265 return ret;
4266}
4267
4276int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val)
4277{
4278 lsm9ds1_int_gen_src_xl_t int_gen_src_xl;
4279 int32_t ret;
4280
4281 ret = lsm9ds1_read_reg(ctx, LSM9DS1_INT_GEN_SRC_XL,
4282 (uint8_t *)&int_gen_src_xl, 1);
4283 val->xl_xl = int_gen_src_xl.xl_xl;
4284 val->xh_xl = int_gen_src_xl.xh_xl;
4285 val->yl_xl = int_gen_src_xl.yl_xl;
4286 val->yh_xl = int_gen_src_xl.yh_xl;
4287 val->zl_xl = int_gen_src_xl.zl_xl;
4288 val->zh_xl = int_gen_src_xl.zh_xl;
4289 val->ia_xl = int_gen_src_xl.ia_xl;
4290
4291 return ret;
4292}
4293
4316int32_t lsm9ds1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4317{
4318 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4319 int32_t ret;
4320
4321 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4322
4323 if (ret == 0)
4324 {
4325 ctrl_reg9.stop_on_fth = (uint8_t)val;
4326 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4327 }
4328
4329 return ret;
4330}
4331
4341int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4342{
4343 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4344 int32_t ret;
4345
4346 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4347 *val = (uint8_t)ctrl_reg9.stop_on_fth;
4348
4349 return ret;
4350}
4351
4360int32_t lsm9ds1_fifo_mode_set(const stmdev_ctx_t *ctx,
4361 lsm9ds1_fifo_md_t val)
4362{
4363 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4364 lsm9ds1_fifo_ctrl_t fifo_ctrl;
4365 int32_t ret;
4366
4367 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4368
4369 if (ret == 0)
4370 {
4371 ctrl_reg9.fifo_en = (((uint8_t)val & 0x10U) >> 4);
4372 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4373 }
4374
4375 if (ret == 0)
4376 {
4377 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4378 }
4379
4380 if (ret == 0)
4381 {
4382 fifo_ctrl.fmode = ((uint8_t)val & 0x0FU);
4383 ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4384 }
4385
4386 return ret;
4387}
4388
4397int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx,
4398 lsm9ds1_fifo_md_t *val)
4399{
4400 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4401 lsm9ds1_fifo_ctrl_t fifo_ctrl;
4402 int32_t ret;
4403
4404 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4405
4406 if (ret == 0)
4407 {
4408 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4409 }
4410
4411 switch ((ctrl_reg9.fifo_en << 4) | ctrl_reg9.fifo_en)
4412 {
4413 case LSM9DS1_FIFO_OFF:
4414 *val = LSM9DS1_FIFO_OFF;
4415 break;
4416
4417 case LSM9DS1_BYPASS_MODE:
4418 *val = LSM9DS1_BYPASS_MODE;
4419 break;
4420
4421 case LSM9DS1_FIFO_MODE:
4422 *val = LSM9DS1_FIFO_MODE;
4423 break;
4424
4425 case LSM9DS1_STREAM_TO_FIFO_MODE:
4426 *val = LSM9DS1_STREAM_TO_FIFO_MODE;
4427 break;
4428
4429 case LSM9DS1_BYPASS_TO_STREAM_MODE:
4430 *val = LSM9DS1_BYPASS_TO_STREAM_MODE;
4431 break;
4432
4433 case LSM9DS1_STREAM_MODE:
4434 *val = LSM9DS1_STREAM_MODE;
4435 break;
4436
4437 default:
4438 *val = LSM9DS1_FIFO_OFF;
4439 break;
4440 }
4441
4442 return ret;
4443}
4444
4453int32_t lsm9ds1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4454{
4455 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4456 int32_t ret;
4457
4458 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4459
4460 if (ret == 0)
4461 {
4462 ctrl_reg9.fifo_temp_en = (uint8_t)val;
4463 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4464 }
4465
4466 return ret;
4467}
4468
4477int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4478{
4479 lsm9ds1_ctrl_reg9_t ctrl_reg9;
4480 int32_t ret;
4481
4482 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG9, (uint8_t *)&ctrl_reg9, 1);
4483 *val = (uint8_t)ctrl_reg9.fifo_temp_en;
4484
4485 return ret;
4486}
4487
4496int32_t lsm9ds1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
4497{
4498 lsm9ds1_fifo_ctrl_t fifo_ctrl;
4499 int32_t ret;
4500
4501 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4502
4503 if (ret == 0)
4504 {
4505 fifo_ctrl.fth = (uint8_t)val;
4506 ret = lsm9ds1_write_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4507 }
4508
4509 return ret;
4510}
4511
4520int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
4521{
4522 lsm9ds1_fifo_ctrl_t fifo_ctrl;
4523 int32_t ret;
4524
4525 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
4526 *val = (uint8_t)fifo_ctrl.fth;
4527
4528 return ret;
4529}
4530
4539int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
4540{
4541 lsm9ds1_fifo_src_t fifo_src;
4542 int32_t ret;
4543
4544 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
4545 *val = fifo_src.fss;
4546
4547 return ret;
4548}
4549
4558int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
4559{
4560 lsm9ds1_fifo_src_t fifo_src;
4561 int32_t ret;
4562
4563 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
4564 *val = fifo_src.fss;
4565
4566 return ret;
4567}
4568
4577int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
4578{
4579 lsm9ds1_fifo_src_t fifo_src;
4580 int32_t ret;
4581
4582 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
4583 *val = fifo_src.ovrn;
4584
4585 return ret;
4586}
4587
4596int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
4597{
4598 lsm9ds1_fifo_src_t fifo_src;
4599 int32_t ret;
4600
4601 ret = lsm9ds1_read_reg(ctx, LSM9DS1_FIFO_SRC, (uint8_t *)&fifo_src, 1);
4602 *val = fifo_src.fth;
4603
4604 return ret;
4605}
4606
4628int32_t lsm9ds1_xl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
4629{
4630 lsm9ds1_ctrl_reg10_t ctrl_reg10;
4631 int32_t ret;
4632
4633 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
4634 (uint8_t *)&ctrl_reg10, 1);
4635
4636 if (ret == 0)
4637 {
4638 ctrl_reg10.st_xl = (uint8_t)val;
4639 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10,
4640 (uint8_t *)&ctrl_reg10, 1);
4641 }
4642
4643 return ret;
4644}
4645
4654int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
4655{
4656 lsm9ds1_ctrl_reg10_t ctrl_reg10;
4657 int32_t ret;
4658
4659 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
4660 (uint8_t *)&ctrl_reg10, 1);
4661 *val = (uint8_t)ctrl_reg10.st_xl;
4662
4663 return ret;
4664}
4665
4674int32_t lsm9ds1_gy_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
4675{
4676 lsm9ds1_ctrl_reg10_t ctrl_reg10;
4677 int32_t ret;
4678
4679 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
4680 (uint8_t *)&ctrl_reg10, 1);
4681
4682 if (ret == 0)
4683 {
4684 ctrl_reg10.st_g = (uint8_t)val;
4685 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG10,
4686 (uint8_t *)&ctrl_reg10, 1);
4687 }
4688
4689 return ret;
4690}
4691
4700int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
4701{
4702 lsm9ds1_ctrl_reg10_t ctrl_reg10;
4703 int32_t ret;
4704
4705 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG10,
4706 (uint8_t *)&ctrl_reg10, 1);
4707 *val = (uint8_t)ctrl_reg10.st_g;
4708
4709 return ret;
4710}
4711
4720int32_t lsm9ds1_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
4721{
4722 lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
4723 int32_t ret;
4724
4725 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
4726 (uint8_t *)&ctrl_reg1_m, 1);
4727
4728 if (ret == 0)
4729 {
4730 ctrl_reg1_m.st = (uint8_t)val;
4731 ret = lsm9ds1_write_reg(ctx, LSM9DS1_CTRL_REG1_M,
4732 (uint8_t *)&ctrl_reg1_m, 1);
4733 }
4734
4735 return ret;
4736}
4737
4746int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
4747{
4748 lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m;
4749 int32_t ret;
4750
4751 ret = lsm9ds1_read_reg(ctx, LSM9DS1_CTRL_REG1_M,
4752 (uint8_t *)&ctrl_reg1_m, 1);
4753 *val = (uint8_t)ctrl_reg1_m.st;
4754
4755 return ret;
4756}
4757
4763/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
lsm9ds1_dev_data_format_set
int32_t lsm9ds1_dev_data_format_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t val)
Big/Little Endian data selection.
Definition lsm9ds1_reg.c:1530
lsm9ds1_dev_reset_get
int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val)
Software reset.
Definition lsm9ds1_reg.c:1500
lsm9ds1_dev_reset_set
int32_t lsm9ds1_dev_reset_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val)
Software reset.
Definition lsm9ds1_reg.c:1457
lsm9ds1_dev_boot_set
int32_t lsm9ds1_dev_boot_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val)
Reboot memory content.
Definition lsm9ds1_reg.c:1617
lsm9ds1_dev_id_get
int32_t lsm9ds1_dev_id_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_id_t *buff)
DeviceWhoamI.
Definition lsm9ds1_reg.c:1403
lsm9ds1_dev_status_get
int32_t lsm9ds1_dev_status_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_status_t *val)
Device status register.
Definition lsm9ds1_reg.c:1430
lsm9ds1_dev_boot_get
int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val)
Reboot memory content.
Definition lsm9ds1_reg.c:1660
lsm9ds1_dev_data_format_get
int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t *val)
Big/Little Endian data selection.
Definition lsm9ds1_reg.c:1573
lsm9ds1_block_data_update_set
int32_t lsm9ds1_block_data_update_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val)
Blockdataupdate.
Definition lsm9ds1_reg.c:804
lsm9ds1_xl_full_scale_set
int32_t lsm9ds1_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val)
Accelerometer full-scale selection.
Definition lsm9ds1_reg.c:733
lsm9ds1_xl_full_scale_get
int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t *val)
Accelerometer full-scale selection.
Definition lsm9ds1_reg.c:760
lsm9ds1_gy_full_scale_get
int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val)
Gyroscope full-scale selection.
Definition lsm9ds1_reg.c:211
lsm9ds1_xl_axis_get
int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val)
Enable accelerometer axis.
Definition lsm9ds1_reg.c:641
lsm9ds1_mag_data_rate_set
int32_t lsm9ds1_mag_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t val)
Magnetometer data rate selection.
Definition lsm9ds1_reg.c:927
lsm9ds1_mag_offset_set
int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
This register is a 16-bit register and represents the X offset used to compensate environmental effec...
Definition lsm9ds1_reg.c:877
lsm9ds1_mag_full_scale_set
int32_t lsm9ds1_mag_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t val)
Magnetometer full Scale Selection.
Definition lsm9ds1_reg.c:1172
lsm9ds1_gy_orient_get
int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val)
Configure gyro orientation.
Definition lsm9ds1_reg.c:479
lsm9ds1_mag_data_rate_get
int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t *val)
Magnetometer data rate selection.
Definition lsm9ds1_reg.c:985
lsm9ds1_mag_full_scale_get
int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t *val)
Magnetometer full scale selection.
Definition lsm9ds1_reg.c:1199
lsm9ds1_gy_full_scale_set
int32_t lsm9ds1_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val)
Gyroscope full-scale selection.
Definition lsm9ds1_reg.c:184
lsm9ds1_xl_axis_set
int32_t lsm9ds1_xl_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val)
Enable accelerometer axis.
Definition lsm9ds1_reg.c:613
lsm9ds1_imu_data_rate_set
int32_t lsm9ds1_imu_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t val)
Data rate selection when both the accelerometer and gyroscope are activated.
Definition lsm9ds1_reg.c:251
lsm9ds1_gy_flag_data_ready_get
int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
Gyroscope new data available.
Definition lsm9ds1_reg.c:524
lsm9ds1_mag_flag_data_ready_get
int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
New data available from magnetometer.
Definition lsm9ds1_reg.c:1242
lsm9ds1_gy_axis_get
int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val)
Enable gyroscope axis.
Definition lsm9ds1_reg.c:592
lsm9ds1_block_data_update_get
int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val)
Blockdataupdate.
Definition lsm9ds1_reg.c:847
lsm9ds1_imu_data_rate_get
int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t *val)
Data rate selection when both the accelerometer and gyroscope are activated.
Definition lsm9ds1_reg.c:307
lsm9ds1_gy_orient_set
int32_t lsm9ds1_gy_orient_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val)
Configure gyro orientation.
Definition lsm9ds1_reg.c:449
lsm9ds1_mag_offset_get
int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
This register is a 16-bit register and represents the X offset used to compensate environmental effec...
Definition lsm9ds1_reg.c:903
lsm9ds1_gy_axis_set
int32_t lsm9ds1_gy_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val)
Enable gyroscope axis.
Definition lsm9ds1_reg.c:566
lsm9ds1_xl_decimation_set
int32_t lsm9ds1_xl_decimation_set(const stmdev_ctx_t *ctx, lsm9ds1_dec_t val)
Decimation of acceleration data on OUT REG and FIFO.
Definition lsm9ds1_reg.c:663
lsm9ds1_xl_decimation_get
int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx, lsm9ds1_dec_t *val)
Decimation of acceleration data on OUT REG and FIFO.
Definition lsm9ds1_reg.c:690
lsm9ds1_xl_flag_data_ready_get
int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
Accelerometer new data available.
Definition lsm9ds1_reg.c:503
lsm9ds1_temp_flag_data_ready_get
int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
Temperature new data available.
Definition lsm9ds1_reg.c:545
lsm9ds1_magnetic_raw_get
int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
Magnetic sensor.
Definition lsm9ds1_reg.c:1347
lsm9ds1_temperature_raw_get
int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
Temperature data output register (r).
Definition lsm9ds1_reg.c:1276
lsm9ds1_magnetic_overflow_get
int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, uint8_t *val)
Internal measurement range overflow on magnetic value.
Definition lsm9ds1_reg.c:1371
lsm9ds1_angular_rate_raw_get
int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
Angular rate sensor.
Definition lsm9ds1_reg.c:1297
lsm9ds1_acceleration_raw_get
int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
Linear acceleration output register.
Definition lsm9ds1_reg.c:1322
lsm9ds1_fifo_stop_on_wtm_get
int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
Sensing chain FIFO stop values memorization at threshold level.
Definition lsm9ds1_reg.c:4341
lsm9ds1_fifo_full_flag_get
int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
FIFOfullstatus.
Definition lsm9ds1_reg.c:4539
lsm9ds1_fifo_data_level_get
int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
Number of unread words (16-bit axes) stored in FIFO.
Definition lsm9ds1_reg.c:4558
lsm9ds1_fifo_temp_batch_get
int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
Batching of temperature data.
Definition lsm9ds1_reg.c:4477
lsm9ds1_fifo_stop_on_wtm_set
int32_t lsm9ds1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
Sensing chain FIFO stop values memorization at threshold level.
Definition lsm9ds1_reg.c:4316
lsm9ds1_fifo_mode_get
int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t *val)
FIFO mode selection.
Definition lsm9ds1_reg.c:4397
lsm9ds1_fifo_mode_set
int32_t lsm9ds1_fifo_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val)
FIFO mode selection.
Definition lsm9ds1_reg.c:4360
lsm9ds1_fifo_temp_batch_set
int32_t lsm9ds1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
Batching of temperature data.
Definition lsm9ds1_reg.c:4453
lsm9ds1_fifo_watermark_get
int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
FIFO watermark level selection.
Definition lsm9ds1_reg.c:4520
lsm9ds1_fifo_ovr_flag_get
int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
FIFO overrun status.
Definition lsm9ds1_reg.c:4577
lsm9ds1_fifo_watermark_set
int32_t lsm9ds1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
FIFO watermark level selection.
Definition lsm9ds1_reg.c:4496
lsm9ds1_fifo_wtm_flag_get
int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
FIFO watermark status.
Definition lsm9ds1_reg.c:4596
lsm9ds1_gy_filter_hp_bandwidth_set
int32_t lsm9ds1_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t val)
Gyroscope high-pass filter bandwidth selection.
Definition lsm9ds1_reg.c:1990
lsm9ds1_gy_filter_int_path_set
int32_t lsm9ds1_gy_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t val)
Gyro interrupt filter path configuration.
Definition lsm9ds1_reg.c:1899
lsm9ds1_xl_filter_hp_bandwidth_get
int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t *val)
Accelerometer digital filter high pass cutoff frequency selection.
Definition lsm9ds1_reg.c:2389
lsm9ds1_gy_filter_hp_bandwidth_get
int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t *val)
Gyroscope high-pass filter bandwidth selection.
Definition lsm9ds1_reg.c:2017
lsm9ds1_xl_filter_out_path_get
int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t *val)
Accelerometer output filter path configuration.
Definition lsm9ds1_reg.c:2248
lsm9ds1_gy_filter_out_path_get
int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t *val)
Gyro output filter path configuration.
Definition lsm9ds1_reg.c:1849
lsm9ds1_filter_settling_mask_get
int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val)
Mask DRDY on pin (both XL & Gyro) until filter settling ends.
Definition lsm9ds1_reg.c:2457
lsm9ds1_gy_filter_lp_bandwidth_set
int32_t lsm9ds1_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t val)
Gyroscope lowpass filter bandwidth selection.
Definition lsm9ds1_reg.c:1738
lsm9ds1_xl_filter_hp_bandwidth_set
int32_t lsm9ds1_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t val)
Accelerometer digital filter high pass cutoff frequency selection.
Definition lsm9ds1_reg.c:2361
lsm9ds1_gy_filter_int_path_get
int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t *val)
Gyro interrupt filter path configuration.
Definition lsm9ds1_reg.c:1940
lsm9ds1_xl_filter_int_path_get
int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t *val)
Definition lsm9ds1_reg.c:2186
lsm9ds1_gy_filter_out_path_set
int32_t lsm9ds1_gy_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t val)
Gyro output filter path configuration.
Definition lsm9ds1_reg.c:1808
lsm9ds1_gy_filter_reference_set
int32_t lsm9ds1_gy_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff)
Reference value for gyroscope’s digital high-pass filter.
Definition lsm9ds1_reg.c:1702
lsm9ds1_xl_filter_aalias_bandwidth_get
int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t *val)
Configure accelerometer anti aliasing filter.
Definition lsm9ds1_reg.c:2112
lsm9ds1_xl_filter_lp_bandwidth_get
int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t *val)
Accelerometer digital filter low pass cutoff frequency selection.
Definition lsm9ds1_reg.c:2313
lsm9ds1_xl_filter_aalias_bandwidth_set
int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t val)
Configure accelerometer anti aliasing filter.
Definition lsm9ds1_reg.c:2084
lsm9ds1_filter_settling_mask_set
int32_t lsm9ds1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
Mask DRDY on pin (both XL & Gyro) until filter settling ends.
Definition lsm9ds1_reg.c:2432
lsm9ds1_xl_filter_int_path_set
int32_t lsm9ds1_xl_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t val)
Configure HP accelerometer filter.
Definition lsm9ds1_reg.c:2159
lsm9ds1_gy_filter_reference_get
int32_t lsm9ds1_gy_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff)
Reference value for gyroscope’s digital high-pass filter.
Definition lsm9ds1_reg.c:1720
lsm9ds1_xl_filter_lp_bandwidth_set
int32_t lsm9ds1_xl_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t val)
Accelerometer digital filter low pass cutoff frequency selection.
Definition lsm9ds1_reg.c:2284
lsm9ds1_xl_filter_out_path_set
int32_t lsm9ds1_xl_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t val)
Accelerometer output filter path configuration.
Definition lsm9ds1_reg.c:2221
lsm9ds1_gy_filter_lp_bandwidth_get
int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t *val)
Gyroscope lowpass filter bandwidth selection.
Definition lsm9ds1_reg.c:1765
lsm9ds1_write_reg
int32_t lsm9ds1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len)
Write generic device register.
Definition lsm9ds1_reg.c:75
lsm9ds1_read_reg
int32_t lsm9ds1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len)
Read generic device register.
Definition lsm9ds1_reg.c:49
lsm9ds1_mag_trshld_axis_get
int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t *val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3855
lsm9ds1_xl_trshld_src_get
int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_src_t *val)
Accelerometer interrupt on threshold source.
Definition lsm9ds1_reg.c:3410
lsm9ds1_mag_trshld_get
int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val)
The value is expressed in 15-bit unsigned.
Definition lsm9ds1_reg.c:3903
lsm9ds1_mag_trshld_axis_set
int32_t lsm9ds1_mag_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3828
lsm9ds1_gy_trshld_min_sample_set
int32_t lsm9ds1_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val)
Enter/exit interrupt duration value.
Definition lsm9ds1_reg.c:3770
lsm9ds1_gy_trshld_mode_set
int32_t lsm9ds1_gy_trshld_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t val)
Decrement or reset counter mode selection.
Definition lsm9ds1_reg.c:3497
lsm9ds1_gy_trshld_mode_get
int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t *val)
Decrement or reset counter mode selection.
Definition lsm9ds1_reg.c:3524
lsm9ds1_gy_trshld_axis_get
int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t *val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3471
lsm9ds1_gy_trshld_x_get
int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val)
Angular rate sensor interrupt threshold on pitch (X) axis.
Definition lsm9ds1_reg.c:3599
lsm9ds1_gy_trshld_x_set
int32_t lsm9ds1_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val)
Angular rate sensor interrupt threshold on pitch (X) axis.
Definition lsm9ds1_reg.c:3559
lsm9ds1_xl_trshld_min_sample_set
int32_t lsm9ds1_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val)
Enter/exit interrupt duration value.
Definition lsm9ds1_reg.c:3324
lsm9ds1_xl_trshld_min_sample_get
int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val)
Enter/exit interrupt duration value.
Definition lsm9ds1_reg.c:3362
lsm9ds1_mag_trshld_src_get
int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_src_t *val)
Magnetometer interrupt on threshold source.
Definition lsm9ds1_reg.c:3877
lsm9ds1_xl_trshld_get
int32_t lsm9ds1_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *buff)
Axis interrupt threshold.
Definition lsm9ds1_reg.c:3307
lsm9ds1_gy_trshld_y_get
int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val)
Angular rate sensor interrupt threshold on roll (Y) axis.
Definition lsm9ds1_reg.c:3670
lsm9ds1_gy_trshld_axis_set
int32_t lsm9ds1_gy_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3438
lsm9ds1_gy_trshld_src_get
int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_src_t *val)
Angular rate sensor interrupt on threshold source.
Definition lsm9ds1_reg.c:3383
lsm9ds1_xl_trshld_axis_get
int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t *val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3264
lsm9ds1_xl_trshld_set
int32_t lsm9ds1_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t *buff)
Axis interrupt threshold.
Definition lsm9ds1_reg.c:3290
lsm9ds1_gy_trshld_y_set
int32_t lsm9ds1_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val)
Angular rate sensor interrupt threshold on roll (Y) axis.
Definition lsm9ds1_reg.c:3630
lsm9ds1_gy_trshld_min_sample_get
int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val)
Enter/exit interrupt duration value.
Definition lsm9ds1_reg.c:3807
lsm9ds1_gy_trshld_z_set
int32_t lsm9ds1_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val)
Angular rate sensor interrupt thresholds on yaw (Z) axis.
Definition lsm9ds1_reg.c:3700
lsm9ds1_xl_trshld_axis_set
int32_t lsm9ds1_xl_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t val)
Enable interrupt generation on threshold event.
Definition lsm9ds1_reg.c:3231
lsm9ds1_gy_trshld_z_get
int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val)
Angular rate sensor interrupt thresholds on yaw (Z) axis.
Definition lsm9ds1_reg.c:3740
lsm9ds1_pin_polarity_get
int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t *val)
Configure the interrupt pin polarity.
Definition lsm9ds1_reg.c:3174
lsm9ds1_pin_logic_set
int32_t lsm9ds1_pin_logic_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val)
AND/OR combination of accelerometer’s interrupt events.
Definition lsm9ds1_reg.c:2722
lsm9ds1_pin_int_m_route_get
int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t *val)
Route a signal on INT_M pin.
Definition lsm9ds1_reg.c:3110
lsm9ds1_pin_int1_route_get
int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t *val)
Route a signal on INT 1_A/G pin.
Definition lsm9ds1_reg.c:2837
lsm9ds1_pin_int2_route_set
int32_t lsm9ds1_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t val)
Route a signal on INT 2_A/G pin.
Definition lsm9ds1_reg.c:2864
lsm9ds1_pin_logic_get
int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t *val)
AND/OR combination of accelerometer’s interrupt events.
Definition lsm9ds1_reg.c:2763
lsm9ds1_pin_mode_get
int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val)
Push-pull/open drain selection on interrupt pads.
Definition lsm9ds1_reg.c:3052
lsm9ds1_pin_polarity_set
int32_t lsm9ds1_pin_polarity_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t val)
Configure the interrupt pin polarity.
Definition lsm9ds1_reg.c:3131
lsm9ds1_pin_int_m_route_set
int32_t lsm9ds1_pin_int_m_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t val)
Route a signal on INT_M pin.
Definition lsm9ds1_reg.c:3085
lsm9ds1_pin_mode_set
int32_t lsm9ds1_pin_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val)
Push-pull/open drain selection on interrupt pads.
Definition lsm9ds1_reg.c:3028
lsm9ds1_pin_notification_set
int32_t lsm9ds1_pin_notification_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t val)
Latched/pulsed interrupt.
Definition lsm9ds1_reg.c:2922
lsm9ds1_pin_int1_route_set
int32_t lsm9ds1_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t val)
Route a signal on INT 1_A/G pin.
Definition lsm9ds1_reg.c:2805
lsm9ds1_pin_notification_get
int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t *val)
Configure the interrupt notification mode.
Definition lsm9ds1_reg.c:2979
lsm9ds1_pin_int2_route_get
int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t *val)
Route a signal on INT 2_A/G pin.
Definition lsm9ds1_reg.c:2895
lsm9ds1_mag_self_test_set
int32_t lsm9ds1_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
Enable/disable self-test mode for magnatic sensor.
Definition lsm9ds1_reg.c:4720
lsm9ds1_gy_self_test_set
int32_t lsm9ds1_gy_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
Enable/disable self-test mode for gyroscope.
Definition lsm9ds1_reg.c:4674
lsm9ds1_xl_self_test_get
int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
Enable/disable self-test mode for accelerometer.
Definition lsm9ds1_reg.c:4654
lsm9ds1_mag_self_test_get
int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
Enable/disable self-test mode for magnatic sensor.
Definition lsm9ds1_reg.c:4746
lsm9ds1_gy_self_test_get
int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
Enable/disable self-test mode for gyroscope.
Definition lsm9ds1_reg.c:4700
lsm9ds1_xl_self_test_set
int32_t lsm9ds1_xl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
Enable/disable self-test mode for accelerometer.
Definition lsm9ds1_reg.c:4628
lsm9ds1_from_fs12gauss_to_mG
float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb)
Definition lsm9ds1_reg.c:148
lsm9ds1_from_fs2g_to_mg
float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb)
Definition lsm9ds1_reg.c:103
lsm9ds1_from_fs245dps_to_mdps
float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb)
Definition lsm9ds1_reg.c:123
lsm9ds1_from_fs16g_to_mg
float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb)
Definition lsm9ds1_reg.c:118
lsm9ds1_from_fs2000dps_to_mdps
float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb)
Definition lsm9ds1_reg.c:133
lsm9ds1_from_fs8g_to_mg
float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb)
Definition lsm9ds1_reg.c:113
lsm9ds1_from_fs4g_to_mg
float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb)
Definition lsm9ds1_reg.c:108
lsm9ds1_from_fs500dps_to_mdps
float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb)
Definition lsm9ds1_reg.c:128
lsm9ds1_from_fs16gauss_to_mG
float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb)
Definition lsm9ds1_reg.c:153
lsm9ds1_from_fs4gauss_to_mG
float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb)
Definition lsm9ds1_reg.c:138
lsm9ds1_from_lsb_to_celsius
float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb)
Definition lsm9ds1_reg.c:158
lsm9ds1_from_fs8gauss_to_mG
float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb)
Definition lsm9ds1_reg.c:143
lsm9ds1_spi_mode_set
int32_t lsm9ds1_spi_mode_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t val)
SPI Serial Interface Mode selection.
Definition lsm9ds1_reg.c:2536
lsm9ds1_auto_increment_set
int32_t lsm9ds1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
Register address automatically incremented during a multiple byte access with a serial interface.
Definition lsm9ds1_reg.c:2491
lsm9ds1_auto_increment_get
int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
Register address automatically incremented during a multiple byte access with a serial interface.
Definition lsm9ds1_reg.c:2516
lsm9ds1_spi_mode_get
int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t *val)
SPI Serial Interface Mode selection.
Definition lsm9ds1_reg.c:2579
lsm9ds1_i2c_interface_set
int32_t lsm9ds1_i2c_interface_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t val)
Enable / Disable I2C interface.
Definition lsm9ds1_reg.c:2623
lsm9ds1_i2c_interface_get
int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t *val)
Enable / Disable I2C interface.
Definition lsm9ds1_reg.c:2666
lsm9ds1_act_duration_get
int32_t lsm9ds1_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *buff)
Inactivity duration in number of sample.
Definition lsm9ds1_reg.c:4083
lsm9ds1_act_duration_set
int32_t lsm9ds1_act_duration_set(const stmdev_ctx_t *ctx, uint8_t *buff)
Inactivity duration in number of sample.
Definition lsm9ds1_reg.c:4066
lsm9ds1_act_mode_set
int32_t lsm9ds1_act_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val)
Gyroscope operating mode during inactivity.
Definition lsm9ds1_reg.c:3989
lsm9ds1_act_threshold_set
int32_t lsm9ds1_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
Inactivity threshold.
Definition lsm9ds1_reg.c:3946
lsm9ds1_6d_mode_get
int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val)
6D feature working mode.
Definition lsm9ds1_reg.c:4188
lsm9ds1_6d_threshold_get
int32_t lsm9ds1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6D functionality axis interrupt threshold.
Definition lsm9ds1_reg.c:4259
lsm9ds1_6d_threshold_set
int32_t lsm9ds1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff)
6D functionality axis interrupt threshold.
Definition lsm9ds1_reg.c:4242
lsm9ds1_6d_src_get
int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val)
Definition lsm9ds1_reg.c:4276
lsm9ds1_act_src_get
int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val)
Inactivity interrupt output signal.
Definition lsm9ds1_reg.c:4100
lsm9ds1_act_mode_get
int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val)
Gyroscope operating mode during inactivity.
Definition lsm9ds1_reg.c:4026
lsm9ds1_6d_mode_set
int32_t lsm9ds1_6d_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val)
6D feature working mode.
Definition lsm9ds1_reg.c:4147
lsm9ds1_act_threshold_get
int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
Inactivity threshold.
Definition lsm9ds1_reg.c:3970
lsm9ds1_mag_fs_t
lsm9ds1_mag_fs_t
Definition lsm9ds1_reg.h:1147
LSM9DS1_CTRL_REG2_M
#define LSM9DS1_CTRL_REG2_M
Definition lsm9ds1_reg.h:721
LSM9DS1_INT_GEN_THS_X_XL
#define LSM9DS1_INT_GEN_THS_X_XL
Definition lsm9ds1_reg.h:227
LSM9DS1_OFFSET_X_REG_L_M
#define LSM9DS1_OFFSET_X_REG_L_M
Definition lsm9ds1_reg.h:695
lsm9ds1_dec_t
lsm9ds1_dec_t
Definition lsm9ds1_reg.h:1069
LSM9DS1_INT_GEN_THS_XH_G
#define LSM9DS1_INT_GEN_THS_XH_G
Definition lsm9ds1_reg.h:632
LSM9DS1_INT_GEN_CFG_G
#define LSM9DS1_INT_GEN_CFG_G
Definition lsm9ds1_reg.h:608
LSM9DS1_INT1_CTRL
#define LSM9DS1_INT1_CTRL
Definition lsm9ds1_reg.h:243
lsm9ds1_lir_t
lsm9ds1_lir_t
Definition lsm9ds1_reg.h:1405
LSM9DS1_CTRL_REG9
#define LSM9DS1_CTRL_REG9
Definition lsm9ds1_reg.h:512
LSM9DS1_OUT_X_L_G
#define LSM9DS1_OUT_X_L_G
Definition lsm9ds1_reg.h:406
LSM9DS1_INT_GEN_THS_ZL_G
#define LSM9DS1_INT_GEN_THS_ZL_G
Definition lsm9ds1_reg.h:678
LSM9DS1_CTRL_REG10
#define LSM9DS1_CTRL_REG10
Definition lsm9ds1_reg.h:536
lsm9ds1_ble_t
lsm9ds1_ble_t
Definition lsm9ds1_reg.h:1198
lsm9ds1_pin_logic_t
lsm9ds1_pin_logic_t
Definition lsm9ds1_reg.h:1365
LSM9DS1_INT_GEN_THS_YL_G
#define LSM9DS1_INT_GEN_THS_YL_G
Definition lsm9ds1_reg.h:661
LSM9DS1_CTRL_REG8
#define LSM9DS1_CTRL_REG8
Definition lsm9ds1_reg.h:488
lsm9ds1_fifo_md_t
lsm9ds1_fifo_md_t
Definition lsm9ds1_reg.h:1610
LSM9DS1_ORIENT_CFG_G
#define LSM9DS1_ORIENT_CFG_G
Definition lsm9ds1_reg.h:338
LSM9DS1_INT_SRC_M
#define LSM9DS1_INT_SRC_M
Definition lsm9ds1_reg.h:843
LSM9DS1_CTRL_REG2_G
#define LSM9DS1_CTRL_REG2_G
Definition lsm9ds1_reg.h:308
LSM9DS1_INT_THS_H_M
#define LSM9DS1_INT_THS_H_M
Definition lsm9ds1_reg.h:873
LSM9DS1_INT_GEN_SRC_XL
#define LSM9DS1_INT_GEN_SRC_XL
Definition lsm9ds1_reg.h:552
__weak
#define __weak
Definition lsm9ds1_reg.h:948
LSM9DS1_STATUS_REG_M
#define LSM9DS1_STATUS_REG_M
Definition lsm9ds1_reg.h:791
lsm9ds1_sim_t
lsm9ds1_sim_t
Definition lsm9ds1_reg.h:1341
LSM9DS1_OUT_TEMP_L
#define LSM9DS1_OUT_TEMP_L
Definition lsm9ds1_reg.h:380
LSM9DS1_INT2_CTRL
#define LSM9DS1_INT2_CTRL
Definition lsm9ds1_reg.h:267
LSM9DS1_CTRL_REG7_XL
#define LSM9DS1_CTRL_REG7_XL
Definition lsm9ds1_reg.h:468
LSM9DS1_FIFO_SRC
#define LSM9DS1_FIFO_SRC
Definition lsm9ds1_reg.h:594
LSM9DS1_INT_GEN_THS_ZH_G
#define LSM9DS1_INT_GEN_THS_ZH_G
Definition lsm9ds1_reg.h:666
LSM9DS1_STATUS_REG
#define LSM9DS1_STATUS_REG
Definition lsm9ds1_reg.h:382
lsm9ds1_xl_out_path_t
lsm9ds1_xl_out_path_t
Definition lsm9ds1_reg.h:1298
lsm9ds1_xl_fs_t
lsm9ds1_xl_fs_t
Definition lsm9ds1_reg.h:1081
lsm9ds1_gy_int_path_t
lsm9ds1_gy_int_path_t
Definition lsm9ds1_reg.h:1246
LSM9DS1_INT_GEN_CFG_XL
#define LSM9DS1_INT_GEN_CFG_XL
Definition lsm9ds1_reg.h:203
lsm9ds1_dcrm_g_t
lsm9ds1_dcrm_g_t
Definition lsm9ds1_reg.h:1507
LSM9DS1_INT_THS_L_M
#define LSM9DS1_INT_THS_L_M
Definition lsm9ds1_reg.h:867
LSM9DS1_ACT_THS
#define LSM9DS1_ACT_THS
Definition lsm9ds1_reg.h:190
lsm9ds1_xl_lp_bw_t
lsm9ds1_xl_lp_bw_t
Definition lsm9ds1_reg.h:1308
LSM9DS1_INT_GEN_THS_YH_G
#define LSM9DS1_INT_GEN_THS_YH_G
Definition lsm9ds1_reg.h:649
lsm9ds1_gy_hp_bw_t
lsm9ds1_gy_hp_bw_t
Definition lsm9ds1_reg.h:1258
lsm9ds1_pp_od_t
lsm9ds1_pp_od_t
Definition lsm9ds1_reg.h:1417
lsm9ds1_act_mode_t
lsm9ds1_act_mode_t
Definition lsm9ds1_reg.h:1560
lsm9ds1_xl_hp_bw_t
lsm9ds1_xl_hp_bw_t
Definition lsm9ds1_reg.h:1321
LSM9DS1_INT_GEN_DUR_XL
#define LSM9DS1_INT_GEN_DUR_XL
Definition lsm9ds1_reg.h:230
lsm9ds1_xl_hp_path_t
lsm9ds1_xl_hp_path_t
Definition lsm9ds1_reg.h:1288
LSM9DS1_FIFO_CTRL
#define LSM9DS1_FIFO_CTRL
Definition lsm9ds1_reg.h:582
LSM9DS1_CTRL_REG5_XL
#define LSM9DS1_CTRL_REG5_XL
Definition lsm9ds1_reg.h:434
LSM9DS1_CTRL_REG1_M
#define LSM9DS1_CTRL_REG1_M
Definition lsm9ds1_reg.h:703
lsm9ds1_6d_mode_t
lsm9ds1_6d_mode_t
Definition lsm9ds1_reg.h:1580
lsm9ds1_mag_data_rate_t
lsm9ds1_mag_data_rate_t
Definition lsm9ds1_reg.h:1101
LSM9DS1_CTRL_REG5_M
#define LSM9DS1_CTRL_REG5_M
Definition lsm9ds1_reg.h:777
LSM9DS1_REFERENCE_G
#define LSM9DS1_REFERENCE_G
Definition lsm9ds1_reg.h:242
LSM9DS1_CTRL_REG3_G
#define LSM9DS1_CTRL_REG3_G
Definition lsm9ds1_reg.h:322
lsm9ds1_imu_odr_t
lsm9ds1_imu_odr_t
Definition lsm9ds1_reg.h:995
LSM9DS1_INT_GEN_DUR_G
#define LSM9DS1_INT_GEN_DUR_G
Definition lsm9ds1_reg.h:683
LSM9DS1_CTRL_REG4
#define LSM9DS1_CTRL_REG4
Definition lsm9ds1_reg.h:412
LSM9DS1_OUT_X_L_M
#define LSM9DS1_OUT_X_L_M
Definition lsm9ds1_reg.h:815
LSM9DS1_CTRL_REG4_M
#define LSM9DS1_CTRL_REG4_M
Definition lsm9ds1_reg.h:761
lsm9ds1_gy_out_path_t
lsm9ds1_gy_out_path_t
Definition lsm9ds1_reg.h:1234
lsm9ds1_inact_t
lsm9ds1_inact_t
Definition lsm9ds1_reg.h:1573
lsm9ds1_i2c_dis_t
lsm9ds1_i2c_dis_t
Definition lsm9ds1_reg.h:1353
lsm9ds1_gy_lp_bw_t
lsm9ds1_gy_lp_bw_t
Definition lsm9ds1_reg.h:1222
lsm9ds1_polarity_t
lsm9ds1_polarity_t
Definition lsm9ds1_reg.h:1433
LSM9DS1_INT_GEN_THS_XL_G
#define LSM9DS1_INT_GEN_THS_XL_G
Definition lsm9ds1_reg.h:644
LSM9DS1_INT_GEN_SRC_G
#define LSM9DS1_INT_GEN_SRC_G
Definition lsm9ds1_reg.h:356
LSM9DS1_CTRL_REG6_XL
#define LSM9DS1_CTRL_REG6_XL
Definition lsm9ds1_reg.h:452
lsm9ds1_gy_fs_t
lsm9ds1_gy_fs_t
Definition lsm9ds1_reg.h:984
LSM9DS1_INT_CFG_M
#define LSM9DS1_INT_CFG_M
Definition lsm9ds1_reg.h:821
LSM9DS1_CTRL_REG1_G
#define LSM9DS1_CTRL_REG1_G
Definition lsm9ds1_reg.h:292
LSM9DS1_ACT_DUR
#define LSM9DS1_ACT_DUR
Definition lsm9ds1_reg.h:202
LSM9DS1_WHO_AM_I
#define LSM9DS1_WHO_AM_I
Definition lsm9ds1_reg.h:291
lsm9ds1_xl_aa_bw_t
lsm9ds1_xl_aa_bw_t
Definition lsm9ds1_reg.h:1276
LSM9DS1_OUT_X_L_XL
#define LSM9DS1_OUT_X_L_XL
Definition lsm9ds1_reg.h:576
LSM9DS1_WHO_AM_I_M
#define LSM9DS1_WHO_AM_I_M
Definition lsm9ds1_reg.h:702
LSM9DS1_CTRL_REG3_M
#define LSM9DS1_CTRL_REG3_M
Definition lsm9ds1_reg.h:741
LSM9DS1_12Ga
@ LSM9DS1_12Ga
Definition lsm9ds1_reg.h:1150
LSM9DS1_4Ga
@ LSM9DS1_4Ga
Definition lsm9ds1_reg.h:1148
LSM9DS1_16Ga
@ LSM9DS1_16Ga
Definition lsm9ds1_reg.h:1151
LSM9DS1_8Ga
@ LSM9DS1_8Ga
Definition lsm9ds1_reg.h:1149
LSM9DS1_NO_DECIMATION
@ LSM9DS1_NO_DECIMATION
Definition lsm9ds1_reg.h:1070
LSM9DS1_EVERY_8_SAMPLES
@ LSM9DS1_EVERY_8_SAMPLES
Definition lsm9ds1_reg.h:1073
LSM9DS1_EVERY_4_SAMPLES
@ LSM9DS1_EVERY_4_SAMPLES
Definition lsm9ds1_reg.h:1072
LSM9DS1_EVERY_2_SAMPLES
@ LSM9DS1_EVERY_2_SAMPLES
Definition lsm9ds1_reg.h:1071
LSM9DS1_INT_LATCHED
@ LSM9DS1_INT_LATCHED
Definition lsm9ds1_reg.h:1407
LSM9DS1_INT_PULSED
@ LSM9DS1_INT_PULSED
Definition lsm9ds1_reg.h:1406
LSM9DS1_MSB_LOW_ADDRESS
@ LSM9DS1_MSB_LOW_ADDRESS
Definition lsm9ds1_reg.h:1200
LSM9DS1_LSB_LOW_ADDRESS
@ LSM9DS1_LSB_LOW_ADDRESS
Definition lsm9ds1_reg.h:1199
LSM9DS1_LOGIC_OR
@ LSM9DS1_LOGIC_OR
Definition lsm9ds1_reg.h:1366
LSM9DS1_LOGIC_AND
@ LSM9DS1_LOGIC_AND
Definition lsm9ds1_reg.h:1367
LSM9DS1_FIFO_OFF
@ LSM9DS1_FIFO_OFF
Definition lsm9ds1_reg.h:1611
LSM9DS1_BYPASS_MODE
@ LSM9DS1_BYPASS_MODE
Definition lsm9ds1_reg.h:1612
LSM9DS1_STREAM_TO_FIFO_MODE
@ LSM9DS1_STREAM_TO_FIFO_MODE
Definition lsm9ds1_reg.h:1614
LSM9DS1_BYPASS_TO_STREAM_MODE
@ LSM9DS1_BYPASS_TO_STREAM_MODE
Definition lsm9ds1_reg.h:1615
LSM9DS1_FIFO_MODE
@ LSM9DS1_FIFO_MODE
Definition lsm9ds1_reg.h:1613
LSM9DS1_STREAM_MODE
@ LSM9DS1_STREAM_MODE
Definition lsm9ds1_reg.h:1616
LSM9DS1_SPI_4_WIRE
@ LSM9DS1_SPI_4_WIRE
Definition lsm9ds1_reg.h:1342
LSM9DS1_SPI_3_WIRE
@ LSM9DS1_SPI_3_WIRE
Definition lsm9ds1_reg.h:1343
LSM9DS1_LP_OUT
@ LSM9DS1_LP_OUT
Definition lsm9ds1_reg.h:1299
LSM9DS1_HP_OUT
@ LSM9DS1_HP_OUT
Definition lsm9ds1_reg.h:1300
LSM9DS1_2g
@ LSM9DS1_2g
Definition lsm9ds1_reg.h:1082
LSM9DS1_4g
@ LSM9DS1_4g
Definition lsm9ds1_reg.h:1084
LSM9DS1_16g
@ LSM9DS1_16g
Definition lsm9ds1_reg.h:1083
LSM9DS1_8g
@ LSM9DS1_8g
Definition lsm9ds1_reg.h:1085
LSM9DS1_LPF1_HPF_INT
@ LSM9DS1_LPF1_HPF_INT
Definition lsm9ds1_reg.h:1248
LSM9DS1_LPF1_HPF_LPF2_INT
@ LSM9DS1_LPF1_HPF_LPF2_INT
Definition lsm9ds1_reg.h:1250
LSM9DS1_LPF1_INT
@ LSM9DS1_LPF1_INT
Definition lsm9ds1_reg.h:1247
LSM9DS1_LPF1_LPF2_INT
@ LSM9DS1_LPF1_LPF2_INT
Definition lsm9ds1_reg.h:1249
LSM9DS1_DECREMENT_MODE
@ LSM9DS1_DECREMENT_MODE
Definition lsm9ds1_reg.h:1509
LSM9DS1_RESET_MODE
@ LSM9DS1_RESET_MODE
Definition lsm9ds1_reg.h:1508
LSM9DS1_LP_ODR_DIV_400
@ LSM9DS1_LP_ODR_DIV_400
Definition lsm9ds1_reg.h:1313
LSM9DS1_LP_ODR_DIV_9
@ LSM9DS1_LP_ODR_DIV_9
Definition lsm9ds1_reg.h:1312
LSM9DS1_LP_ODR_DIV_100
@ LSM9DS1_LP_ODR_DIV_100
Definition lsm9ds1_reg.h:1311
LSM9DS1_LP_DISABLE
@ LSM9DS1_LP_DISABLE
Definition lsm9ds1_reg.h:1309
LSM9DS1_LP_ODR_DIV_50
@ LSM9DS1_LP_ODR_DIV_50
Definition lsm9ds1_reg.h:1310
LSM9DS1_HP_LIGHT
@ LSM9DS1_HP_LIGHT
Definition lsm9ds1_reg.h:1267
LSM9DS1_HP_EXTREME
@ LSM9DS1_HP_EXTREME
Definition lsm9ds1_reg.h:1259
LSM9DS1_HP_ULTRA_STRONG
@ LSM9DS1_HP_ULTRA_STRONG
Definition lsm9ds1_reg.h:1260
LSM9DS1_HP_ULTRA_LIGHT
@ LSM9DS1_HP_ULTRA_LIGHT
Definition lsm9ds1_reg.h:1268
LSM9DS1_HP_MEDIUM
@ LSM9DS1_HP_MEDIUM
Definition lsm9ds1_reg.h:1264
LSM9DS1_HP_LOW
@ LSM9DS1_HP_LOW
Definition lsm9ds1_reg.h:1265
LSM9DS1_HP_STRONG
@ LSM9DS1_HP_STRONG
Definition lsm9ds1_reg.h:1261
LSM9DS1_HP_HIGH
@ LSM9DS1_HP_HIGH
Definition lsm9ds1_reg.h:1263
LSM9DS1_HP_ULTRA_LOW
@ LSM9DS1_HP_ULTRA_LOW
Definition lsm9ds1_reg.h:1266
LSM9DS1_HP_ULTRA_HIGH
@ LSM9DS1_HP_ULTRA_HIGH
Definition lsm9ds1_reg.h:1262
LSM9DS1_OPEN_DRAIN
@ LSM9DS1_OPEN_DRAIN
Definition lsm9ds1_reg.h:1419
LSM9DS1_PUSH_PULL
@ LSM9DS1_PUSH_PULL
Definition lsm9ds1_reg.h:1418
LSM9DS1_GYRO_POWER_DOWN
@ LSM9DS1_GYRO_POWER_DOWN
Definition lsm9ds1_reg.h:1561
LSM9DS1_GYRO_SLEEP
@ LSM9DS1_GYRO_SLEEP
Definition lsm9ds1_reg.h:1562
LSM9DS1_HP_ODR_DIV_100
@ LSM9DS1_HP_ODR_DIV_100
Definition lsm9ds1_reg.h:1323
LSM9DS1_HP_ODR_DIV_9
@ LSM9DS1_HP_ODR_DIV_9
Definition lsm9ds1_reg.h:1324
LSM9DS1_HP_ODR_DIV_400
@ LSM9DS1_HP_ODR_DIV_400
Definition lsm9ds1_reg.h:1325
LSM9DS1_HP_ODR_DIV_50
@ LSM9DS1_HP_ODR_DIV_50
Definition lsm9ds1_reg.h:1322
LSM9DS1_HP_DIS
@ LSM9DS1_HP_DIS
Definition lsm9ds1_reg.h:1289
LSM9DS1_HP_EN
@ LSM9DS1_HP_EN
Definition lsm9ds1_reg.h:1290
LSM9DS1_POS_MOVE_RECO_DISABLE
@ LSM9DS1_POS_MOVE_RECO_DISABLE
Definition lsm9ds1_reg.h:1581
LSM9DS1_4D_POS_RECO
@ LSM9DS1_4D_POS_RECO
Definition lsm9ds1_reg.h:1585
LSM9DS1_6D_MOVE_RECO
@ LSM9DS1_6D_MOVE_RECO
Definition lsm9ds1_reg.h:1582
LSM9DS1_6D_POS_RECO
@ LSM9DS1_6D_POS_RECO
Definition lsm9ds1_reg.h:1584
LSM9DS1_4D_MOVE_RECO
@ LSM9DS1_4D_MOVE_RECO
Definition lsm9ds1_reg.h:1583
LSM9DS1_MAG_LP_20Hz
@ LSM9DS1_MAG_LP_20Hz
Definition lsm9ds1_reg.h:1108
LSM9DS1_MAG_HP_1Hz25
@ LSM9DS1_MAG_HP_1Hz25
Definition lsm9ds1_reg.h:1120
LSM9DS1_MAG_MP_560Hz
@ LSM9DS1_MAG_MP_560Hz
Definition lsm9ds1_reg.h:1137
LSM9DS1_MAG_LP_80Hz
@ LSM9DS1_MAG_LP_80Hz
Definition lsm9ds1_reg.h:1110
LSM9DS1_MAG_UHP_80Hz
@ LSM9DS1_MAG_UHP_80Hz
Definition lsm9ds1_reg.h:1134
LSM9DS1_MAG_MP_1Hz25
@ LSM9DS1_MAG_MP_1Hz25
Definition lsm9ds1_reg.h:1112
LSM9DS1_MAG_MP_40Hz
@ LSM9DS1_MAG_MP_40Hz
Definition lsm9ds1_reg.h:1117
LSM9DS1_MAG_LP_5Hz
@ LSM9DS1_MAG_LP_5Hz
Definition lsm9ds1_reg.h:1106
LSM9DS1_MAG_HP_40Hz
@ LSM9DS1_MAG_HP_40Hz
Definition lsm9ds1_reg.h:1125
LSM9DS1_MAG_UHP_10Hz
@ LSM9DS1_MAG_UHP_10Hz
Definition lsm9ds1_reg.h:1131
LSM9DS1_MAG_HP_80Hz
@ LSM9DS1_MAG_HP_80Hz
Definition lsm9ds1_reg.h:1126
LSM9DS1_MAG_MP_20Hz
@ LSM9DS1_MAG_MP_20Hz
Definition lsm9ds1_reg.h:1116
LSM9DS1_MAG_ONE_SHOT
@ LSM9DS1_MAG_ONE_SHOT
Definition lsm9ds1_reg.h:1139
LSM9DS1_MAG_MP_5Hz
@ LSM9DS1_MAG_MP_5Hz
Definition lsm9ds1_reg.h:1114
LSM9DS1_MAG_LP_2Hz5
@ LSM9DS1_MAG_LP_2Hz5
Definition lsm9ds1_reg.h:1105
LSM9DS1_MAG_UHP_1Hz25
@ LSM9DS1_MAG_UHP_1Hz25
Definition lsm9ds1_reg.h:1128
LSM9DS1_MAG_MP_10Hz
@ LSM9DS1_MAG_MP_10Hz
Definition lsm9ds1_reg.h:1115
LSM9DS1_MAG_MP_2Hz5
@ LSM9DS1_MAG_MP_2Hz5
Definition lsm9ds1_reg.h:1113
LSM9DS1_MAG_LP_40Hz
@ LSM9DS1_MAG_LP_40Hz
Definition lsm9ds1_reg.h:1109
LSM9DS1_MAG_UHP_40Hz
@ LSM9DS1_MAG_UHP_40Hz
Definition lsm9ds1_reg.h:1133
LSM9DS1_MAG_POWER_DOWN
@ LSM9DS1_MAG_POWER_DOWN
Definition lsm9ds1_reg.h:1102
LSM9DS1_MAG_HP_5Hz
@ LSM9DS1_MAG_HP_5Hz
Definition lsm9ds1_reg.h:1122
LSM9DS1_MAG_LP_1Hz25
@ LSM9DS1_MAG_LP_1Hz25
Definition lsm9ds1_reg.h:1104
LSM9DS1_MAG_UHP_155Hz
@ LSM9DS1_MAG_UHP_155Hz
Definition lsm9ds1_reg.h:1135
LSM9DS1_MAG_HP_300Hz
@ LSM9DS1_MAG_HP_300Hz
Definition lsm9ds1_reg.h:1136
LSM9DS1_MAG_MP_0Hz625
@ LSM9DS1_MAG_MP_0Hz625
Definition lsm9ds1_reg.h:1111
LSM9DS1_MAG_LP_1000Hz
@ LSM9DS1_MAG_LP_1000Hz
Definition lsm9ds1_reg.h:1138
LSM9DS1_MAG_LP_10Hz
@ LSM9DS1_MAG_LP_10Hz
Definition lsm9ds1_reg.h:1107
LSM9DS1_MAG_UHP_20Hz
@ LSM9DS1_MAG_UHP_20Hz
Definition lsm9ds1_reg.h:1132
LSM9DS1_MAG_UHP_2Hz5
@ LSM9DS1_MAG_UHP_2Hz5
Definition lsm9ds1_reg.h:1129
LSM9DS1_MAG_HP_10Hz
@ LSM9DS1_MAG_HP_10Hz
Definition lsm9ds1_reg.h:1123
LSM9DS1_MAG_UHP_5Hz
@ LSM9DS1_MAG_UHP_5Hz
Definition lsm9ds1_reg.h:1130
LSM9DS1_MAG_UHP_0Hz625
@ LSM9DS1_MAG_UHP_0Hz625
Definition lsm9ds1_reg.h:1127
LSM9DS1_MAG_MP_80Hz
@ LSM9DS1_MAG_MP_80Hz
Definition lsm9ds1_reg.h:1118
LSM9DS1_MAG_LP_0Hz625
@ LSM9DS1_MAG_LP_0Hz625
Definition lsm9ds1_reg.h:1103
LSM9DS1_MAG_HP_20Hz
@ LSM9DS1_MAG_HP_20Hz
Definition lsm9ds1_reg.h:1124
LSM9DS1_MAG_HP_0Hz625
@ LSM9DS1_MAG_HP_0Hz625
Definition lsm9ds1_reg.h:1119
LSM9DS1_MAG_HP_2Hz5
@ LSM9DS1_MAG_HP_2Hz5
Definition lsm9ds1_reg.h:1121
LSM9DS1_GY_OFF_XL_952Hz
@ LSM9DS1_GY_OFF_XL_952Hz
Definition lsm9ds1_reg.h:1002
LSM9DS1_XL_OFF_GY_59Hz5_LP
@ LSM9DS1_XL_OFF_GY_59Hz5_LP
Definition lsm9ds1_reg.h:1016
LSM9DS1_IMU_59Hz5_LP
@ LSM9DS1_IMU_59Hz5_LP
Definition lsm9ds1_reg.h:1019
LSM9DS1_IMU_14Hz9_LP
@ LSM9DS1_IMU_14Hz9_LP
Definition lsm9ds1_reg.h:1018
LSM9DS1_GY_OFF_XL_50Hz
@ LSM9DS1_GY_OFF_XL_50Hz
Definition lsm9ds1_reg.h:998
LSM9DS1_XL_OFF_GY_14Hz9_LP
@ LSM9DS1_XL_OFF_GY_14Hz9_LP
Definition lsm9ds1_reg.h:1015
LSM9DS1_IMU_OFF
@ LSM9DS1_IMU_OFF
Definition lsm9ds1_reg.h:996
LSM9DS1_IMU_119Hz
@ LSM9DS1_IMU_119Hz
Definition lsm9ds1_reg.h:1011
LSM9DS1_XL_OFF_GY_476Hz
@ LSM9DS1_XL_OFF_GY_476Hz
Definition lsm9ds1_reg.h:1007
LSM9DS1_GY_OFF_XL_238Hz
@ LSM9DS1_GY_OFF_XL_238Hz
Definition lsm9ds1_reg.h:1000
LSM9DS1_IMU_59Hz5
@ LSM9DS1_IMU_59Hz5
Definition lsm9ds1_reg.h:1010
LSM9DS1_IMU_14Hz9
@ LSM9DS1_IMU_14Hz9
Definition lsm9ds1_reg.h:1009
LSM9DS1_XL_OFF_GY_119Hz_LP
@ LSM9DS1_XL_OFF_GY_119Hz_LP
Definition lsm9ds1_reg.h:1017
LSM9DS1_XL_OFF_GY_59Hz5
@ LSM9DS1_XL_OFF_GY_59Hz5
Definition lsm9ds1_reg.h:1004
LSM9DS1_GY_OFF_XL_476Hz
@ LSM9DS1_GY_OFF_XL_476Hz
Definition lsm9ds1_reg.h:1001
LSM9DS1_XL_OFF_GY_119Hz
@ LSM9DS1_XL_OFF_GY_119Hz
Definition lsm9ds1_reg.h:1005
LSM9DS1_XL_OFF_GY_238Hz
@ LSM9DS1_XL_OFF_GY_238Hz
Definition lsm9ds1_reg.h:1006
LSM9DS1_IMU_238Hz
@ LSM9DS1_IMU_238Hz
Definition lsm9ds1_reg.h:1012
LSM9DS1_IMU_119Hz_LP
@ LSM9DS1_IMU_119Hz_LP
Definition lsm9ds1_reg.h:1020
LSM9DS1_IMU_952Hz
@ LSM9DS1_IMU_952Hz
Definition lsm9ds1_reg.h:1014
LSM9DS1_XL_OFF_GY_14Hz9
@ LSM9DS1_XL_OFF_GY_14Hz9
Definition lsm9ds1_reg.h:1003
LSM9DS1_GY_OFF_XL_119Hz
@ LSM9DS1_GY_OFF_XL_119Hz
Definition lsm9ds1_reg.h:999
LSM9DS1_XL_OFF_GY_952Hz
@ LSM9DS1_XL_OFF_GY_952Hz
Definition lsm9ds1_reg.h:1008
LSM9DS1_IMU_476Hz
@ LSM9DS1_IMU_476Hz
Definition lsm9ds1_reg.h:1013
LSM9DS1_GY_OFF_XL_10Hz
@ LSM9DS1_GY_OFF_XL_10Hz
Definition lsm9ds1_reg.h:997
LSM9DS1_LPF1_LPF2_OUT
@ LSM9DS1_LPF1_LPF2_OUT
Definition lsm9ds1_reg.h:1237
LSM9DS1_LPF1_HPF_OUT
@ LSM9DS1_LPF1_HPF_OUT
Definition lsm9ds1_reg.h:1236
LSM9DS1_LPF1_OUT
@ LSM9DS1_LPF1_OUT
Definition lsm9ds1_reg.h:1235
LSM9DS1_LPF1_HPF_LPF2_OUT
@ LSM9DS1_LPF1_HPF_LPF2_OUT
Definition lsm9ds1_reg.h:1238
LSM9DS1_INACTIVITY
@ LSM9DS1_INACTIVITY
Definition lsm9ds1_reg.h:1575
LSM9DS1_ACTIVITY
@ LSM9DS1_ACTIVITY
Definition lsm9ds1_reg.h:1574
LSM9DS1_I2C_ENABLE
@ LSM9DS1_I2C_ENABLE
Definition lsm9ds1_reg.h:1354
LSM9DS1_I2C_DISABLE
@ LSM9DS1_I2C_DISABLE
Definition lsm9ds1_reg.h:1355
LSM9DS1_LP_LIGHT
@ LSM9DS1_LP_LIGHT
Definition lsm9ds1_reg.h:1225
LSM9DS1_LP_STRONG
@ LSM9DS1_LP_STRONG
Definition lsm9ds1_reg.h:1223
LSM9DS1_LP_MEDIUM
@ LSM9DS1_LP_MEDIUM
Definition lsm9ds1_reg.h:1224
LSM9DS1_LP_ULTRA_LIGHT
@ LSM9DS1_LP_ULTRA_LIGHT
Definition lsm9ds1_reg.h:1226
LSM9DS1_ACTIVE_HIGH
@ LSM9DS1_ACTIVE_HIGH
Definition lsm9ds1_reg.h:1435
LSM9DS1_ACTIVE_LOW
@ LSM9DS1_ACTIVE_LOW
Definition lsm9ds1_reg.h:1434
LSM9DS1_245dps
@ LSM9DS1_245dps
Definition lsm9ds1_reg.h:985
LSM9DS1_2000dps
@ LSM9DS1_2000dps
Definition lsm9ds1_reg.h:987
LSM9DS1_500dps
@ LSM9DS1_500dps
Definition lsm9ds1_reg.h:986
LSM9DS1_AUTO
@ LSM9DS1_AUTO
Definition lsm9ds1_reg.h:1277
LSM9DS1_50Hz
@ LSM9DS1_50Hz
Definition lsm9ds1_reg.h:1281
LSM9DS1_105Hz
@ LSM9DS1_105Hz
Definition lsm9ds1_reg.h:1280
LSM9DS1_408Hz
@ LSM9DS1_408Hz
Definition lsm9ds1_reg.h:1278
LSM9DS1_211Hz
@ LSM9DS1_211Hz
Definition lsm9ds1_reg.h:1279
PROPERTY_ENABLE
#define PROPERTY_ENABLE
Definition lsm9ds1_reg.h:102
PROPERTY_DISABLE
#define PROPERTY_DISABLE
Definition lsm9ds1_reg.h:101
lsm9ds1_reg.h
This file contains all the functions prototypes for the lsm9ds1_reg.c driver.
lsm9ds1_6d_src_t
Definition lsm9ds1_reg.h:1595
lsm9ds1_6d_src_t::yh_xl
uint8_t yh_xl
Definition lsm9ds1_reg.h:1599
lsm9ds1_6d_src_t::yl_xl
uint8_t yl_xl
Definition lsm9ds1_reg.h:1598
lsm9ds1_6d_src_t::ia_xl
uint8_t ia_xl
Definition lsm9ds1_reg.h:1602
lsm9ds1_6d_src_t::zh_xl
uint8_t zh_xl
Definition lsm9ds1_reg.h:1601
lsm9ds1_6d_src_t::xh_xl
uint8_t xh_xl
Definition lsm9ds1_reg.h:1597
lsm9ds1_6d_src_t::zl_xl
uint8_t zl_xl
Definition lsm9ds1_reg.h:1600
lsm9ds1_6d_src_t::xl_xl
uint8_t xl_xl
Definition lsm9ds1_reg.h:1596
lsm9ds1_act_ths_t
Definition lsm9ds1_reg.h:192
lsm9ds1_act_ths_t::sleep_on_inact_en
uint8_t sleep_on_inact_en
Definition lsm9ds1_reg.h:195
lsm9ds1_act_ths_t::act_ths
uint8_t act_ths
Definition lsm9ds1_reg.h:194
lsm9ds1_ctrl_reg10_t
Definition lsm9ds1_reg.h:538
lsm9ds1_ctrl_reg10_t::st_g
uint8_t st_g
Definition lsm9ds1_reg.h:542
lsm9ds1_ctrl_reg10_t::st_xl
uint8_t st_xl
Definition lsm9ds1_reg.h:540
lsm9ds1_ctrl_reg1_g_t
Definition lsm9ds1_reg.h:294
lsm9ds1_ctrl_reg1_g_t::bw_g
uint8_t bw_g
Definition lsm9ds1_reg.h:296
lsm9ds1_ctrl_reg1_g_t::fs_g
uint8_t fs_g
Definition lsm9ds1_reg.h:298
lsm9ds1_ctrl_reg1_g_t::odr_g
uint8_t odr_g
Definition lsm9ds1_reg.h:299
lsm9ds1_ctrl_reg1_m_t
Definition lsm9ds1_reg.h:705
lsm9ds1_ctrl_reg1_m_t::temp_comp
uint8_t temp_comp
Definition lsm9ds1_reg.h:711
lsm9ds1_ctrl_reg1_m_t::om
uint8_t om
Definition lsm9ds1_reg.h:710
lsm9ds1_ctrl_reg1_m_t::fast_odr
uint8_t fast_odr
Definition lsm9ds1_reg.h:708
lsm9ds1_ctrl_reg1_m_t::st
uint8_t st
Definition lsm9ds1_reg.h:707
lsm9ds1_ctrl_reg1_m_t::_do
uint8_t _do
Definition lsm9ds1_reg.h:709
lsm9ds1_ctrl_reg2_g_t
Definition lsm9ds1_reg.h:310
lsm9ds1_ctrl_reg2_g_t::out_sel
uint8_t out_sel
Definition lsm9ds1_reg.h:312
lsm9ds1_ctrl_reg2_g_t::int_sel
uint8_t int_sel
Definition lsm9ds1_reg.h:313
lsm9ds1_ctrl_reg2_m_t
Definition lsm9ds1_reg.h:723
lsm9ds1_ctrl_reg2_m_t::soft_rst
uint8_t soft_rst
Definition lsm9ds1_reg.h:726
lsm9ds1_ctrl_reg2_m_t::fs
uint8_t fs
Definition lsm9ds1_reg.h:729
lsm9ds1_ctrl_reg2_m_t::reboot
uint8_t reboot
Definition lsm9ds1_reg.h:727
lsm9ds1_ctrl_reg3_g_t
Definition lsm9ds1_reg.h:324
lsm9ds1_ctrl_reg3_g_t::hpcf_g
uint8_t hpcf_g
Definition lsm9ds1_reg.h:326
lsm9ds1_ctrl_reg3_g_t::lp_mode
uint8_t lp_mode
Definition lsm9ds1_reg.h:329
lsm9ds1_ctrl_reg3_g_t::hp_en
uint8_t hp_en
Definition lsm9ds1_reg.h:328
lsm9ds1_ctrl_reg3_m_t
Definition lsm9ds1_reg.h:743
lsm9ds1_ctrl_reg3_m_t::i2c_disable
uint8_t i2c_disable
Definition lsm9ds1_reg.h:750
lsm9ds1_ctrl_reg3_m_t::sim
uint8_t sim
Definition lsm9ds1_reg.h:746
lsm9ds1_ctrl_reg3_m_t::md
uint8_t md
Definition lsm9ds1_reg.h:745
lsm9ds1_ctrl_reg4_m_t
Definition lsm9ds1_reg.h:763
lsm9ds1_ctrl_reg4_m_t::ble
uint8_t ble
Definition lsm9ds1_reg.h:766
lsm9ds1_ctrl_reg4_m_t::omz
uint8_t omz
Definition lsm9ds1_reg.h:767
lsm9ds1_ctrl_reg4_t
Definition lsm9ds1_reg.h:414
lsm9ds1_ctrl_reg4_t::lir_xl1
uint8_t lir_xl1
Definition lsm9ds1_reg.h:417
lsm9ds1_ctrl_reg4_t::yen_g
uint8_t yen_g
Definition lsm9ds1_reg.h:420
lsm9ds1_ctrl_reg4_t::zen_g
uint8_t zen_g
Definition lsm9ds1_reg.h:421
lsm9ds1_ctrl_reg4_t::_4d_xl1
uint8_t _4d_xl1
Definition lsm9ds1_reg.h:416
lsm9ds1_ctrl_reg4_t::xen_g
uint8_t xen_g
Definition lsm9ds1_reg.h:419
lsm9ds1_ctrl_reg5_m_t
Definition lsm9ds1_reg.h:779
lsm9ds1_ctrl_reg5_m_t::bdu
uint8_t bdu
Definition lsm9ds1_reg.h:782
lsm9ds1_ctrl_reg5_m_t::fast_read
uint8_t fast_read
Definition lsm9ds1_reg.h:783
lsm9ds1_ctrl_reg5_xl_t
Definition lsm9ds1_reg.h:436
lsm9ds1_ctrl_reg5_xl_t::zen_xl
uint8_t zen_xl
Definition lsm9ds1_reg.h:441
lsm9ds1_ctrl_reg5_xl_t::dec
uint8_t dec
Definition lsm9ds1_reg.h:442
lsm9ds1_ctrl_reg5_xl_t::yen_xl
uint8_t yen_xl
Definition lsm9ds1_reg.h:440
lsm9ds1_ctrl_reg5_xl_t::xen_xl
uint8_t xen_xl
Definition lsm9ds1_reg.h:439
lsm9ds1_ctrl_reg6_xl_t
Definition lsm9ds1_reg.h:454
lsm9ds1_ctrl_reg6_xl_t::odr_xl
uint8_t odr_xl
Definition lsm9ds1_reg.h:459
lsm9ds1_ctrl_reg6_xl_t::bw_scal_odr
uint8_t bw_scal_odr
Definition lsm9ds1_reg.h:457
lsm9ds1_ctrl_reg6_xl_t::fs_xl
uint8_t fs_xl
Definition lsm9ds1_reg.h:458
lsm9ds1_ctrl_reg6_xl_t::bw_xl
uint8_t bw_xl
Definition lsm9ds1_reg.h:456
lsm9ds1_ctrl_reg7_xl_t
Definition lsm9ds1_reg.h:470
lsm9ds1_ctrl_reg7_xl_t::dcf
uint8_t dcf
Definition lsm9ds1_reg.h:476
lsm9ds1_ctrl_reg7_xl_t::fds
uint8_t fds
Definition lsm9ds1_reg.h:474
lsm9ds1_ctrl_reg7_xl_t::hpis1
uint8_t hpis1
Definition lsm9ds1_reg.h:472
lsm9ds1_ctrl_reg7_xl_t::hr
uint8_t hr
Definition lsm9ds1_reg.h:477
lsm9ds1_ctrl_reg8_t
Definition lsm9ds1_reg.h:490
lsm9ds1_ctrl_reg8_t::boot
uint8_t boot
Definition lsm9ds1_reg.h:499
lsm9ds1_ctrl_reg8_t::pp_od
uint8_t pp_od
Definition lsm9ds1_reg.h:496
lsm9ds1_ctrl_reg8_t::if_add_inc
uint8_t if_add_inc
Definition lsm9ds1_reg.h:494
lsm9ds1_ctrl_reg8_t::sim
uint8_t sim
Definition lsm9ds1_reg.h:495
lsm9ds1_ctrl_reg8_t::ble
uint8_t ble
Definition lsm9ds1_reg.h:493
lsm9ds1_ctrl_reg8_t::bdu
uint8_t bdu
Definition lsm9ds1_reg.h:498
lsm9ds1_ctrl_reg8_t::h_lactive
uint8_t h_lactive
Definition lsm9ds1_reg.h:497
lsm9ds1_ctrl_reg8_t::sw_reset
uint8_t sw_reset
Definition lsm9ds1_reg.h:492
lsm9ds1_ctrl_reg9_t
Definition lsm9ds1_reg.h:514
lsm9ds1_ctrl_reg9_t::sleep_g
uint8_t sleep_g
Definition lsm9ds1_reg.h:522
lsm9ds1_ctrl_reg9_t::drdy_mask_bit
uint8_t drdy_mask_bit
Definition lsm9ds1_reg.h:519
lsm9ds1_ctrl_reg9_t::i2c_disable
uint8_t i2c_disable
Definition lsm9ds1_reg.h:518
lsm9ds1_ctrl_reg9_t::fifo_en
uint8_t fifo_en
Definition lsm9ds1_reg.h:517
lsm9ds1_ctrl_reg9_t::fifo_temp_en
uint8_t fifo_temp_en
Definition lsm9ds1_reg.h:520
lsm9ds1_ctrl_reg9_t::stop_on_fth
uint8_t stop_on_fth
Definition lsm9ds1_reg.h:516
lsm9ds1_fifo_ctrl_t
Definition lsm9ds1_reg.h:584
lsm9ds1_fifo_ctrl_t::fth
uint8_t fth
Definition lsm9ds1_reg.h:586
lsm9ds1_fifo_ctrl_t::fmode
uint8_t fmode
Definition lsm9ds1_reg.h:587
lsm9ds1_fifo_src_t
Definition lsm9ds1_reg.h:596
lsm9ds1_fifo_src_t::ovrn
uint8_t ovrn
Definition lsm9ds1_reg.h:599
lsm9ds1_fifo_src_t::fss
uint8_t fss
Definition lsm9ds1_reg.h:598
lsm9ds1_fifo_src_t::fth
uint8_t fth
Definition lsm9ds1_reg.h:600
lsm9ds1_gy_axis_t
Definition lsm9ds1_reg.h:1049
lsm9ds1_gy_axis_t::zen_g
uint8_t zen_g
Definition lsm9ds1_reg.h:1052
lsm9ds1_gy_axis_t::xen_g
uint8_t xen_g
Definition lsm9ds1_reg.h:1050
lsm9ds1_gy_axis_t::yen_g
uint8_t yen_g
Definition lsm9ds1_reg.h:1051
lsm9ds1_gy_orient_t
Definition lsm9ds1_reg.h:1028
lsm9ds1_gy_orient_t::signx_g
uint8_t signx_g
Definition lsm9ds1_reg.h:1032
lsm9ds1_gy_orient_t::orient
uint8_t orient
Definition lsm9ds1_reg.h:1029
lsm9ds1_gy_orient_t::signy_g
uint8_t signy_g
Definition lsm9ds1_reg.h:1031
lsm9ds1_gy_orient_t::signz_g
uint8_t signz_g
Definition lsm9ds1_reg.h:1030
lsm9ds1_gy_trshld_en_t
Definition lsm9ds1_reg.h:1493
lsm9ds1_gy_trshld_en_t::yhie_g
uint8_t yhie_g
Definition lsm9ds1_reg.h:1497
lsm9ds1_gy_trshld_en_t::xhie_g
uint8_t xhie_g
Definition lsm9ds1_reg.h:1495
lsm9ds1_gy_trshld_en_t::xlie_g
uint8_t xlie_g
Definition lsm9ds1_reg.h:1494
lsm9ds1_gy_trshld_en_t::zhie_g
uint8_t zhie_g
Definition lsm9ds1_reg.h:1499
lsm9ds1_gy_trshld_en_t::ylie_g
uint8_t ylie_g
Definition lsm9ds1_reg.h:1496
lsm9ds1_gy_trshld_en_t::zlie_g
uint8_t zlie_g
Definition lsm9ds1_reg.h:1498
lsm9ds1_gy_trshld_src_t
Definition lsm9ds1_reg.h:1467
lsm9ds1_gy_trshld_src_t::zh_g
uint8_t zh_g
Definition lsm9ds1_reg.h:1473
lsm9ds1_gy_trshld_src_t::xh_g
uint8_t xh_g
Definition lsm9ds1_reg.h:1469
lsm9ds1_gy_trshld_src_t::ia_g
uint8_t ia_g
Definition lsm9ds1_reg.h:1474
lsm9ds1_gy_trshld_src_t::zl_g
uint8_t zl_g
Definition lsm9ds1_reg.h:1472
lsm9ds1_gy_trshld_src_t::xl_g
uint8_t xl_g
Definition lsm9ds1_reg.h:1468
lsm9ds1_gy_trshld_src_t::yl_g
uint8_t yl_g
Definition lsm9ds1_reg.h:1470
lsm9ds1_gy_trshld_src_t::yh_g
uint8_t yh_g
Definition lsm9ds1_reg.h:1471
lsm9ds1_id_t
Definition lsm9ds1_reg.h:1173
lsm9ds1_id_t::mag
uint8_t mag
Definition lsm9ds1_reg.h:1175
lsm9ds1_id_t::imu
uint8_t imu
Definition lsm9ds1_reg.h:1174
lsm9ds1_int1_ctrl_t
Definition lsm9ds1_reg.h:245
lsm9ds1_int1_ctrl_t::int1_fss5
uint8_t int1_fss5
Definition lsm9ds1_reg.h:252
lsm9ds1_int1_ctrl_t::int1_ovr
uint8_t int1_ovr
Definition lsm9ds1_reg.h:251
lsm9ds1_int1_ctrl_t::int1_ig_g
uint8_t int1_ig_g
Definition lsm9ds1_reg.h:254
lsm9ds1_int1_ctrl_t::int1_drdy_xl
uint8_t int1_drdy_xl
Definition lsm9ds1_reg.h:247
lsm9ds1_int1_ctrl_t::int1_ig_xl
uint8_t int1_ig_xl
Definition lsm9ds1_reg.h:253
lsm9ds1_int1_ctrl_t::int1_drdy_g
uint8_t int1_drdy_g
Definition lsm9ds1_reg.h:248
lsm9ds1_int1_ctrl_t::int1_boot
uint8_t int1_boot
Definition lsm9ds1_reg.h:249
lsm9ds1_int1_ctrl_t::int1_fth
uint8_t int1_fth
Definition lsm9ds1_reg.h:250
lsm9ds1_int2_ctrl_t
Definition lsm9ds1_reg.h:269
lsm9ds1_int2_ctrl_t::int2_drdy_g
uint8_t int2_drdy_g
Definition lsm9ds1_reg.h:272
lsm9ds1_int2_ctrl_t::int2_drdy_temp
uint8_t int2_drdy_temp
Definition lsm9ds1_reg.h:273
lsm9ds1_int2_ctrl_t::int2_ovr
uint8_t int2_ovr
Definition lsm9ds1_reg.h:275
lsm9ds1_int2_ctrl_t::int2_inact
uint8_t int2_inact
Definition lsm9ds1_reg.h:278
lsm9ds1_int2_ctrl_t::int2_fth
uint8_t int2_fth
Definition lsm9ds1_reg.h:274
lsm9ds1_int2_ctrl_t::int2_drdy_xl
uint8_t int2_drdy_xl
Definition lsm9ds1_reg.h:271
lsm9ds1_int2_ctrl_t::int2_fss5
uint8_t int2_fss5
Definition lsm9ds1_reg.h:276
lsm9ds1_int_cfg_m_t
Definition lsm9ds1_reg.h:823
lsm9ds1_int_cfg_m_t::xien
uint8_t xien
Definition lsm9ds1_reg.h:831
lsm9ds1_int_cfg_m_t::iea
uint8_t iea
Definition lsm9ds1_reg.h:827
lsm9ds1_int_cfg_m_t::iel
uint8_t iel
Definition lsm9ds1_reg.h:826
lsm9ds1_int_cfg_m_t::yien
uint8_t yien
Definition lsm9ds1_reg.h:830
lsm9ds1_int_cfg_m_t::zien
uint8_t zien
Definition lsm9ds1_reg.h:829
lsm9ds1_int_cfg_m_t::ien
uint8_t ien
Definition lsm9ds1_reg.h:825
lsm9ds1_int_gen_cfg_g_t
Definition lsm9ds1_reg.h:610
lsm9ds1_int_gen_cfg_g_t::yhie_g
uint8_t yhie_g
Definition lsm9ds1_reg.h:615
lsm9ds1_int_gen_cfg_g_t::xlie_g
uint8_t xlie_g
Definition lsm9ds1_reg.h:612
lsm9ds1_int_gen_cfg_g_t::zhie_g
uint8_t zhie_g
Definition lsm9ds1_reg.h:617
lsm9ds1_int_gen_cfg_g_t::xhie_g
uint8_t xhie_g
Definition lsm9ds1_reg.h:613
lsm9ds1_int_gen_cfg_g_t::ylie_g
uint8_t ylie_g
Definition lsm9ds1_reg.h:614
lsm9ds1_int_gen_cfg_g_t::aoi_g
uint8_t aoi_g
Definition lsm9ds1_reg.h:619
lsm9ds1_int_gen_cfg_g_t::zlie_g
uint8_t zlie_g
Definition lsm9ds1_reg.h:616
lsm9ds1_int_gen_cfg_g_t::lir_g
uint8_t lir_g
Definition lsm9ds1_reg.h:618
lsm9ds1_int_gen_cfg_xl_t
Definition lsm9ds1_reg.h:205
lsm9ds1_int_gen_cfg_xl_t::aoi_xl
uint8_t aoi_xl
Definition lsm9ds1_reg.h:214
lsm9ds1_int_gen_cfg_xl_t::zhie_xl
uint8_t zhie_xl
Definition lsm9ds1_reg.h:212
lsm9ds1_int_gen_cfg_xl_t::xlie_xl
uint8_t xlie_xl
Definition lsm9ds1_reg.h:207
lsm9ds1_int_gen_cfg_xl_t::zlie_xl
uint8_t zlie_xl
Definition lsm9ds1_reg.h:211
lsm9ds1_int_gen_cfg_xl_t::xhie_xl
uint8_t xhie_xl
Definition lsm9ds1_reg.h:208
lsm9ds1_int_gen_cfg_xl_t::ylie_xl
uint8_t ylie_xl
Definition lsm9ds1_reg.h:209
lsm9ds1_int_gen_cfg_xl_t::yhie_xl
uint8_t yhie_xl
Definition lsm9ds1_reg.h:210
lsm9ds1_int_gen_cfg_xl_t::_6d
uint8_t _6d
Definition lsm9ds1_reg.h:213
lsm9ds1_int_gen_dur_g_t
Definition lsm9ds1_reg.h:685
lsm9ds1_int_gen_dur_g_t::wait_g
uint8_t wait_g
Definition lsm9ds1_reg.h:688
lsm9ds1_int_gen_dur_g_t::dur_g
uint8_t dur_g
Definition lsm9ds1_reg.h:687
lsm9ds1_int_gen_dur_xl_t
Definition lsm9ds1_reg.h:232
lsm9ds1_int_gen_dur_xl_t::dur_xl
uint8_t dur_xl
Definition lsm9ds1_reg.h:234
lsm9ds1_int_gen_dur_xl_t::wait_xl
uint8_t wait_xl
Definition lsm9ds1_reg.h:235
lsm9ds1_int_gen_src_g_t
Definition lsm9ds1_reg.h:358
lsm9ds1_int_gen_src_g_t::zh_g
uint8_t zh_g
Definition lsm9ds1_reg.h:365
lsm9ds1_int_gen_src_g_t::zl_g
uint8_t zl_g
Definition lsm9ds1_reg.h:364
lsm9ds1_int_gen_src_g_t::xh_g
uint8_t xh_g
Definition lsm9ds1_reg.h:361
lsm9ds1_int_gen_src_g_t::yl_g
uint8_t yl_g
Definition lsm9ds1_reg.h:362
lsm9ds1_int_gen_src_g_t::yh_g
uint8_t yh_g
Definition lsm9ds1_reg.h:363
lsm9ds1_int_gen_src_g_t::xl_g
uint8_t xl_g
Definition lsm9ds1_reg.h:360
lsm9ds1_int_gen_src_g_t::ia_g
uint8_t ia_g
Definition lsm9ds1_reg.h:366
lsm9ds1_int_gen_src_xl_t
Definition lsm9ds1_reg.h:554
lsm9ds1_int_gen_src_xl_t::xl_xl
uint8_t xl_xl
Definition lsm9ds1_reg.h:556
lsm9ds1_int_gen_src_xl_t::yl_xl
uint8_t yl_xl
Definition lsm9ds1_reg.h:558
lsm9ds1_int_gen_src_xl_t::yh_xl
uint8_t yh_xl
Definition lsm9ds1_reg.h:559
lsm9ds1_int_gen_src_xl_t::zh_xl
uint8_t zh_xl
Definition lsm9ds1_reg.h:561
lsm9ds1_int_gen_src_xl_t::zl_xl
uint8_t zl_xl
Definition lsm9ds1_reg.h:560
lsm9ds1_int_gen_src_xl_t::ia_xl
uint8_t ia_xl
Definition lsm9ds1_reg.h:562
lsm9ds1_int_gen_src_xl_t::xh_xl
uint8_t xh_xl
Definition lsm9ds1_reg.h:557
lsm9ds1_int_gen_ths_xh_g_t
Definition lsm9ds1_reg.h:634
lsm9ds1_int_gen_ths_xh_g_t::ths_g_x
uint8_t ths_g_x
Definition lsm9ds1_reg.h:636
lsm9ds1_int_gen_ths_xh_g_t::dcrm_g
uint8_t dcrm_g
Definition lsm9ds1_reg.h:637
lsm9ds1_int_gen_ths_xl_g_t
Definition lsm9ds1_reg.h:646
lsm9ds1_int_gen_ths_xl_g_t::ths_g_x
uint8_t ths_g_x
Definition lsm9ds1_reg.h:647
lsm9ds1_int_gen_ths_yh_g_t
Definition lsm9ds1_reg.h:651
lsm9ds1_int_gen_ths_yh_g_t::ths_g_y
uint8_t ths_g_y
Definition lsm9ds1_reg.h:653
lsm9ds1_int_gen_ths_yl_g_t
Definition lsm9ds1_reg.h:663
lsm9ds1_int_gen_ths_yl_g_t::ths_g_y
uint8_t ths_g_y
Definition lsm9ds1_reg.h:664
lsm9ds1_int_gen_ths_zh_g_t
Definition lsm9ds1_reg.h:668
lsm9ds1_int_gen_ths_zh_g_t::ths_g_z
uint8_t ths_g_z
Definition lsm9ds1_reg.h:670
lsm9ds1_int_gen_ths_zl_g_t
Definition lsm9ds1_reg.h:680
lsm9ds1_int_gen_ths_zl_g_t::ths_g_z
uint8_t ths_g_z
Definition lsm9ds1_reg.h:681
lsm9ds1_int_src_m_t
Definition lsm9ds1_reg.h:845
lsm9ds1_int_src_m_t::nth_y
uint8_t nth_y
Definition lsm9ds1_reg.h:850
lsm9ds1_int_src_m_t::nth_x
uint8_t nth_x
Definition lsm9ds1_reg.h:851
lsm9ds1_int_src_m_t::pth_x
uint8_t pth_x
Definition lsm9ds1_reg.h:854
lsm9ds1_int_src_m_t::nth_z
uint8_t nth_z
Definition lsm9ds1_reg.h:849
lsm9ds1_int_src_m_t::pth_z
uint8_t pth_z
Definition lsm9ds1_reg.h:852
lsm9ds1_int_src_m_t::_int
uint8_t _int
Definition lsm9ds1_reg.h:847
lsm9ds1_int_src_m_t::pth_y
uint8_t pth_y
Definition lsm9ds1_reg.h:853
lsm9ds1_int_src_m_t::mroi
uint8_t mroi
Definition lsm9ds1_reg.h:848
lsm9ds1_int_ths_h_m_t
Definition lsm9ds1_reg.h:875
lsm9ds1_int_ths_h_m_t::ths
uint8_t ths
Definition lsm9ds1_reg.h:877
lsm9ds1_int_ths_l_m_t
Definition lsm9ds1_reg.h:869
lsm9ds1_int_ths_l_m_t::ths
uint8_t ths
Definition lsm9ds1_reg.h:870
lsm9ds1_mag_trshld_axis_t
Definition lsm9ds1_reg.h:1531
lsm9ds1_mag_trshld_axis_t::xien
uint8_t xien
Definition lsm9ds1_reg.h:1534
lsm9ds1_mag_trshld_axis_t::yien
uint8_t yien
Definition lsm9ds1_reg.h:1533
lsm9ds1_mag_trshld_axis_t::zien
uint8_t zien
Definition lsm9ds1_reg.h:1532
lsm9ds1_mag_trshld_src_t
Definition lsm9ds1_reg.h:1541
lsm9ds1_mag_trshld_src_t::pth_x
uint8_t pth_x
Definition lsm9ds1_reg.h:1548
lsm9ds1_mag_trshld_src_t::pth_y
uint8_t pth_y
Definition lsm9ds1_reg.h:1547
lsm9ds1_mag_trshld_src_t::nth_z
uint8_t nth_z
Definition lsm9ds1_reg.h:1543
lsm9ds1_mag_trshld_src_t::pth_z
uint8_t pth_z
Definition lsm9ds1_reg.h:1546
lsm9ds1_mag_trshld_src_t::_int
uint8_t _int
Definition lsm9ds1_reg.h:1542
lsm9ds1_mag_trshld_src_t::nth_x
uint8_t nth_x
Definition lsm9ds1_reg.h:1545
lsm9ds1_mag_trshld_src_t::nth_y
uint8_t nth_y
Definition lsm9ds1_reg.h:1544
lsm9ds1_orient_cfg_g_t
Definition lsm9ds1_reg.h:340
lsm9ds1_orient_cfg_g_t::signy_g
uint8_t signy_g
Definition lsm9ds1_reg.h:344
lsm9ds1_orient_cfg_g_t::signz_g
uint8_t signz_g
Definition lsm9ds1_reg.h:343
lsm9ds1_orient_cfg_g_t::signx_g
uint8_t signx_g
Definition lsm9ds1_reg.h:345
lsm9ds1_orient_cfg_g_t::orient
uint8_t orient
Definition lsm9ds1_reg.h:342
lsm9ds1_pin_int1_route_t
Definition lsm9ds1_reg.h:1375
lsm9ds1_pin_int1_route_t::int1_fth
uint8_t int1_fth
Definition lsm9ds1_reg.h:1379
lsm9ds1_pin_int1_route_t::int1_drdy_g
uint8_t int1_drdy_g
Definition lsm9ds1_reg.h:1377
lsm9ds1_pin_int1_route_t::int1_ig_xl
uint8_t int1_ig_xl
Definition lsm9ds1_reg.h:1382
lsm9ds1_pin_int1_route_t::int1_ovr
uint8_t int1_ovr
Definition lsm9ds1_reg.h:1380
lsm9ds1_pin_int1_route_t::int1_fss5
uint8_t int1_fss5
Definition lsm9ds1_reg.h:1381
lsm9ds1_pin_int1_route_t::int1_boot
uint8_t int1_boot
Definition lsm9ds1_reg.h:1378
lsm9ds1_pin_int1_route_t::int1_drdy_xl
uint8_t int1_drdy_xl
Definition lsm9ds1_reg.h:1376
lsm9ds1_pin_int1_route_t::int1_ig_g
uint8_t int1_ig_g
Definition lsm9ds1_reg.h:1383
lsm9ds1_pin_int2_route_t
Definition lsm9ds1_reg.h:1390
lsm9ds1_pin_int2_route_t::int2_ovr
uint8_t int2_ovr
Definition lsm9ds1_reg.h:1395
lsm9ds1_pin_int2_route_t::int2_fth
uint8_t int2_fth
Definition lsm9ds1_reg.h:1394
lsm9ds1_pin_int2_route_t::int2_drdy_xl
uint8_t int2_drdy_xl
Definition lsm9ds1_reg.h:1391
lsm9ds1_pin_int2_route_t::int2_drdy_temp
uint8_t int2_drdy_temp
Definition lsm9ds1_reg.h:1393
lsm9ds1_pin_int2_route_t::int2_inact
uint8_t int2_inact
Definition lsm9ds1_reg.h:1397
lsm9ds1_pin_int2_route_t::int2_fss5
uint8_t int2_fss5
Definition lsm9ds1_reg.h:1396
lsm9ds1_pin_int2_route_t::int2_drdy_g
uint8_t int2_drdy_g
Definition lsm9ds1_reg.h:1392
lsm9ds1_pin_m_route_t
Definition lsm9ds1_reg.h:1425
lsm9ds1_pin_m_route_t::ien
uint8_t ien
Definition lsm9ds1_reg.h:1426
lsm9ds1_status_reg_m_t
Definition lsm9ds1_reg.h:793
lsm9ds1_status_reg_m_t::zyxda
uint8_t zyxda
Definition lsm9ds1_reg.h:798
lsm9ds1_status_reg_t
Definition lsm9ds1_reg.h:384
lsm9ds1_status_reg_t::inact
uint8_t inact
Definition lsm9ds1_reg.h:390
lsm9ds1_status_reg_t::xlda
uint8_t xlda
Definition lsm9ds1_reg.h:386
lsm9ds1_status_reg_t::tda
uint8_t tda
Definition lsm9ds1_reg.h:388
lsm9ds1_status_reg_t::gda
uint8_t gda
Definition lsm9ds1_reg.h:387
lsm9ds1_status_t
Definition lsm9ds1_reg.h:1182
lsm9ds1_status_t::status_mag
lsm9ds1_status_reg_m_t status_mag
Definition lsm9ds1_reg.h:1183
lsm9ds1_status_t::status_imu
lsm9ds1_status_reg_t status_imu
Definition lsm9ds1_reg.h:1184
lsm9ds1_xl_axis_t
Definition lsm9ds1_reg.h:1059
lsm9ds1_xl_axis_t::zen_xl
uint8_t zen_xl
Definition lsm9ds1_reg.h:1062
lsm9ds1_xl_axis_t::xen_xl
uint8_t xen_xl
Definition lsm9ds1_reg.h:1060
lsm9ds1_xl_axis_t::yen_xl
uint8_t yen_xl
Definition lsm9ds1_reg.h:1061
lsm9ds1_xl_trshld_en_t
Definition lsm9ds1_reg.h:1445
lsm9ds1_xl_trshld_en_t::xhie_xl
uint8_t xhie_xl
Definition lsm9ds1_reg.h:1447
lsm9ds1_xl_trshld_en_t::yhie_xl
uint8_t yhie_xl
Definition lsm9ds1_reg.h:1449
lsm9ds1_xl_trshld_en_t::zlie_xl
uint8_t zlie_xl
Definition lsm9ds1_reg.h:1450
lsm9ds1_xl_trshld_en_t::ylie_xl
uint8_t ylie_xl
Definition lsm9ds1_reg.h:1448
lsm9ds1_xl_trshld_en_t::xlie_xl
uint8_t xlie_xl
Definition lsm9ds1_reg.h:1446
lsm9ds1_xl_trshld_en_t::zhie_xl
uint8_t zhie_xl
Definition lsm9ds1_reg.h:1451
lsm9ds1_xl_trshld_src_t
Definition lsm9ds1_reg.h:1480
lsm9ds1_xl_trshld_src_t::xh_xl
uint8_t xh_xl
Definition lsm9ds1_reg.h:1482
lsm9ds1_xl_trshld_src_t::zh_xl
uint8_t zh_xl
Definition lsm9ds1_reg.h:1486
lsm9ds1_xl_trshld_src_t::yl_xl
uint8_t yl_xl
Definition lsm9ds1_reg.h:1483
lsm9ds1_xl_trshld_src_t::zl_xl
uint8_t zl_xl
Definition lsm9ds1_reg.h:1485
lsm9ds1_xl_trshld_src_t::xl_xl
uint8_t xl_xl
Definition lsm9ds1_reg.h:1481
lsm9ds1_xl_trshld_src_t::yh_xl
uint8_t yh_xl
Definition lsm9ds1_reg.h:1484
lsm9ds1_xl_trshld_src_t::ia_xl
uint8_t ia_xl
Definition lsm9ds1_reg.h:1487
stmdev_ctx_t
Definition lsm9ds1_reg.h:117
stmdev_ctx_t::read_reg
stmdev_read_ptr read_reg
Definition lsm9ds1_reg.h:120
stmdev_ctx_t::write_reg
stmdev_write_ptr write_reg
Component mandatory fields.
Definition lsm9ds1_reg.h:119
stmdev_ctx_t::handle
void * handle
Customizable optional pointer.
Definition lsm9ds1_reg.h:124